luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

added another VLSI logo and fixed control port numbering

This commit is contained in:
Jesse Cirimelli-Low 2018-11-11 07:22:13 -08:00
parent aadf160ce4
commit 5c4ee911aa
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/characterizer/lib.py
View File

@ -569,7 +569,7 @@ class lib:
for port in self.all_ports:
#CSb timings
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format(
"CSb{1}[{0}:0]".format(self.sram.word_size - 1, port),
"CSb{0}".format(port),
min(list(map(round_time,self.times["setup_times_LH"]))),
max(list(map(round_time,self.times["setup_times_LH"]))),
@ -608,7 +608,7 @@ class lib:
#WEb timings
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},".format(
"WEb{1}[{0}:0]".format(self.sram.word_size - 1, port),
"WEb{0}".format(port),
min(list(map(round_time,self.times["setup_times_LH"]))),
max(list(map(round_time,self.times["setup_times_LH"]))),

2
compiler/datasheet/datasheet.py
View File

@ -41,7 +41,7 @@ class datasheet():
LVS = 'skipped'
PEX = 'skipped'
self.html +='<img src=' + os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/vlsi_logo.png alt="VLSIDA" />'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>'+ self.name + '.html' + '</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>'+ 'DRC: ' + str(DRC) + '</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>'+ 'LVS: ' + str(LVS) + '</p>'