mirror of https://github.com/VLSIDA/OpenRAM.git
Remove old setup.tcl and edit one in tech dir
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@ -99,26 +99,6 @@ def write_netgen_script(cell_name, sp_name):
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f.close()
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os.system("chmod u+x {}".format(run_file))
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setup_file = OPTS.openram_temp + "setup.tcl"
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f = open(setup_file, "w")
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f.write("ignore class c\n")
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f.write("equate class {{nfet {0}.spice}} {{n {1}}}\n".format(cell_name, sp_name))
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f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name))
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# This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
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# Is there a more elegant way to add this when needed?
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f.write("flatten class {{{0}.spice bitcell_array}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name))
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f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
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f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
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f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name))
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f.write("property {{p {0}}} remove as ad ps pd\n".format(sp_name))
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f.write("permute transistors\n")
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f.write("permute pins n source drain\n")
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f.write("permute pins p source drain\n")
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f.close()
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def run_drc(cell_name, gds_name, extract=False, final_verification=False):
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"""Run DRC check on a cell which is implemented in gds_name."""
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@ -4,6 +4,7 @@ equate class {-circuit1 nfet} {-circuit2 n}
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equate class {-circuit1 pfet} {-circuit2 p}
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# This circuit has symmetries and needs to be flattened to resolve them
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# or the banks won't pass
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flatten class {-circuit1 bitcell_array}
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flatten class {-circuit1 precharge_array_1}
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flatten class {-circuit1 precharge_array_2}
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flatten class {-circuit1 precharge_array_3}
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