Correcting functional inheritance from simulation.

This commit is contained in:
Michael Timothy Grimes 2018-10-04 13:55:59 -07:00
parent e258199fa3
commit cf4b216888
2 changed files with 4 additions and 4 deletions

View File

@ -19,7 +19,7 @@ class functional(simulation):
"""
def __init__(self, sram, spfile, corner):
super().__init__(sram, spfile, corner)
simulation.__init__(self, sram, spfile, corner)
self.set_corner(corner)
self.set_spice_constants()

View File

@ -64,10 +64,10 @@ class stimuli():
for readwrite_port in range(readwrite_num):
self.sf.write("WEB{0} ".format(readwrite_port))
for port in range(total_port_num):
self.sf.write("CLK{0} ".format(port))
#for port in range(total_port_num):
# self.sf.write("CLK{0} ".format(port))
#self.sf.write("{0} ".format(tech.spice["clk"]))
self.sf.write("{0} ".format(tech.spice["clk"]))
for read_output in read_ports:
for i in range(dbits):
self.sf.write("DOUT{0}[{1}] ".format(read_output, i))