mirror of https://github.com/VLSIDA/OpenRAM.git
Enable psram 1rw 2mux layout test.
This commit is contained in:
Matt Guthaus
parent
f04e76a54f
commit
2e5ae70391
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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class psram_1bank_2mux_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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# testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.num_words=32
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux with control logic")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -1,136 +0,0 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
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class sram_1bank_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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# testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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c = sram_config(word_size=4,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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c.num_words=32
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux with control logic")
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a = sram(c, "sram2")
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self.local_check(a, final_verification=True)
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"""
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c.num_words=64
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c.words_per_row=4
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debug.info(1, "Single bank, four way column mux with control logic")
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a = sram(c, "sram3")
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self.local_check(a, final_verification=True)
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c.word_size=2
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c.num_words=128
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c.words_per_row=8
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debug.info(1, "Single bank, eight way column mux with control logic")
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a = sram(c, "sram4")
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self.local_check(a, final_verification=True)
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# testing sram using pbitcell in various port combinations
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# layout for multiple ports does not work yet
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"""
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OPTS.netlist_only = True
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c.num_words=16
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c.words_per_row=1
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OPTS.num_rw_ports = 2
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 2
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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"""
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OPTS.num_rw_ports = 0
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 2
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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OPTS.num_rw_ports = 2
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 2
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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OPTS.num_rw_ports = 2
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 0
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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OPTS.num_rw_ports = 2
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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# testing with various column muxes
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OPTS.num_rw_ports = c.num_rw_ports = 2
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OPTS.num_w_ports = c.num_w_ports = 2
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OPTS.num_r_ports = c.num_r_ports = 2
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c.num_words=32
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c.words_per_row=2
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debug.info(1, "Single bank two way column mux with control logic")
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a = sram(c, "sram2")
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self.local_check(a, final_verification=True)
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c.num_words=64
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c.words_per_row=4
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debug.info(1, "Single bank, four way column mux with control logic")
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a = sram(c, "sram3")
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self.local_check(a, final_verification=True)
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c.word_size=2
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c.num_words=128
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c.words_per_row=8
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debug.info(1, "Single bank, eight way column mux with control logic")
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a = sram(c, "sram4")
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self.local_check(a, final_verification=True)
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"""
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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