mirror of https://github.com/VLSIDA/OpenRAM.git
updating debug messages in functional test
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8a56dd2ac9
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@ -97,13 +97,16 @@ class functional():
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self.sp_read_value[port] = "0" + self.sp_read_value[port]
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else:
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self.functional_fail = 1
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self.error ="FAILED: dout value ({}) does not fall within noise margins.".format(self.sp_read_value[port])
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self.error ="FAILED: dout value {0} does not fall within noise margins <{1} or >{2}.".format(value,0.25*self.vdd_voltage,0.75*self.vdd_voltage)
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if i < self.num_checks:
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self.read_values_over_test[i].append(self.sp_read_value[port])
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else:
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self.read_values_test[i-self.num_checks].append(self.sp_read_value[port])
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if self.functional_fail:
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return (self.functional_fail, self.error)
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# Compare written values to read values
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for i in range(self.num_checks):
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debug.info(1, "Stored Word - Overwrite Test: {}".format(self.stored_values_over_test[i]))
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@ -147,7 +150,7 @@ class functional():
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self.sp_read_value[port] = "0" + self.sp_read_value[port]
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else:
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self.functional_fail = 1
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self.error ="FAILED: dout value ({}) does not fall within noise margins.".format(self.sp_read_value[port])
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self.error ="FAILED: dout value {0} does not fall within noise margins <{1} or >{2}.".format(value,0.25*self.vdd_voltage,0.75*self.vdd_voltage)
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if i < self.num_checks:
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self.read_values_multi_test[i][self.multi_addrs[i][port]] = self.sp_read_value[port]
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@ -155,6 +158,9 @@ class functional():
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self.read_values_over_test[i-self.num_checks].append(self.sp_read_value[port])
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else:
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self.read_values_test[i-2*self.num_checks].append(self.sp_read_value[port])
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if self.functional_fail:
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return (self.functional_fail, self.error)
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# Compare written values to read values
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for i in range(self.num_checks):
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@ -36,24 +36,9 @@ class psram_func_test(openram_test):
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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"""
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f.run()
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"""
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 1
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OPTS.num_w_ports = 2
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OPTS.num_r_ports = 2
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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