mirror of https://github.com/VLSIDA/OpenRAM.git
Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation
This commit is contained in:
Hunter Nichols
parent
a3bec5518c
commit
3ac2d29940
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@ -7,8 +7,9 @@ from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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from .simulation import simulation
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class delay():
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class delay(simulation):
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"""Functions to measure the delay and power of an SRAM at a given address and
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data bit.
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@ -26,27 +27,14 @@ class delay():
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"""
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.num_cols = self.sram.num_cols
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self.num_rows = self.sram.num_rows
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self.num_banks = self.sram.num_banks
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self.sp_file = spfile
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self.total_ports = self.sram.total_ports
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self.total_write = self.sram.total_write
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self.total_read = self.sram.total_read
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self.read_index = self.sram.read_index
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self.write_index = self.sram.write_index
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self.port_id = self.sram.port_id
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simulation.__init__(self, sram, spfile, corner)
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# These are the member variables for a simulation
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self.targ_read_ports = []
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self.targ_write_ports = []
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self.period = 0
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self.set_load_slew(0,0)
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self.set_corner(corner)
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self.create_port_names()
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self.create_signal_names()
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#Create global measure names. Should maybe be an input at some point.
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@ -66,34 +54,6 @@ class delay():
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#This is TODO once multiport control has been finalized.
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#self.control_name = "CSB"
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def create_port_names(self):
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"""Generates the port names to be used in characterization and sets default simulation target ports"""
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self.write_ports = []
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self.read_ports = []
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self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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#save a member variable to avoid accessing global. readwrite ports have different control signals.
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self.readwrite_port_num = OPTS.num_rw_ports
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#Generate the port names. readwrite ports are required to be added first for this to work.
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for readwrite_port_num in range(OPTS.num_rw_ports):
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self.read_ports.append(readwrite_port_num)
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self.write_ports.append(readwrite_port_num)
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#This placement is intentional. It makes indexing input data easier. See self.data_values
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for write_port_num in range(OPTS.num_rw_ports, OPTS.num_rw_ports+OPTS.num_w_ports):
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self.write_ports.append(write_port_num)
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for read_port_num in range(OPTS.num_rw_ports+OPTS.num_w_ports, OPTS.num_rw_ports+OPTS.num_w_ports+OPTS.num_r_ports):
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self.read_ports.append(read_port_num)
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#Set the default target ports for simulation. Default is all the ports.
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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def set_corner(self,corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_load_slew(self,load,slew):
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""" Set the load and slew """
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self.load = load
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@ -113,9 +73,9 @@ class delay():
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debug.error("Given probe_data is not an integer to specify a data bit",1)
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#Adding port options here which the characterizer cannot handle. Some may be added later like ROM
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if len(self.read_ports) == 0:
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if len(self.read_index) == 0:
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debug.error("Characterizer does not currently support SRAMs without read ports.",1)
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if len(self.write_ports) == 0:
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if len(self.write_index) == 0:
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debug.error("Characterizer does not currently support SRAMs without write ports.",1)
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def write_generic_stimulus(self):
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@ -129,12 +89,12 @@ class delay():
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_sram(sram=self.sram,
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port_signal_names=(self.addr_name,self.din_name,self.dout_name),
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port_info=(self.total_port_num,self.write_ports,self.read_ports),
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port_info=(self.total_ports,self.write_index,self.read_index),
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abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.sf.write("\n* SRAM output loads\n")
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for port in self.read_ports:
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for port in self.read_index:
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for i in range(self.word_size):
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self.sf.write("CD{0}{1} {2}{0}_{1} 0 {3}f\n".format(port,i,self.dout_name,self.load))
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@ -172,7 +132,7 @@ class delay():
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self.gen_control()
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self.sf.write("\n* Generation of Port clock signal\n")
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for port in range(self.total_port_num):
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for port in range(self.total_ports):
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self.stim.gen_pulse(sig_name="CLK{0}".format(port),
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v1=0,
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v2=self.vdd_voltage,
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@ -214,24 +174,24 @@ class delay():
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# generate data and addr signals
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self.sf.write("\n* Generation of data and address signals\n")
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for write_port in self.write_ports:
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for write_port in self.write_index:
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for i in range(self.word_size):
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self.stim.gen_constant(sig_name="{0}{1}_{2} ".format(self.din_name,write_port, i),
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v_val=0)
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for port in range(self.total_port_num):
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for port in range(self.total_ports):
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for i in range(self.addr_size):
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self.stim.gen_constant(sig_name="{0}{1}_{2}".format(self.addr_name,port, i),
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v_val=0)
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# generate control signals
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self.sf.write("\n* Generation of control signals\n")
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for port in range(self.total_port_num):
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for port in range(self.total_ports):
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self.stim.gen_constant(sig_name="CSB{0}".format(port), v_val=self.vdd_voltage)
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if port in self.write_ports and port in self.read_ports:
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if port in self.write_index and port in self.read_index:
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self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage)
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self.sf.write("\n* Generation of global clock signal\n")
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for port in range(self.total_port_num):
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for port in range(self.total_ports):
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self.stim.gen_constant(sig_name="CLK{0}".format(port), v_val=0)
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self.write_power_measures()
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@ -360,10 +320,9 @@ class delay():
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double the period until we find a valid period to use as a
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starting point.
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"""
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debug.check(port in self.read_ports, "Characterizer requires a read port to determine a period.")
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debug.check(port in self.read_index, "Characterizer requires a read port to determine a period.")
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feasible_period = float(tech.spice["feasible_period"])
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#feasible_period = float(2.5)#What happens if feasible starting point is wrong?
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time_out = 9
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while True:
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time_out -= 1
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@ -406,19 +365,18 @@ class delay():
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Loops through all read ports determining the feasible period and collecting
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delay information from each port.
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"""
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feasible_delays = [{} for i in range(self.total_port_num)]
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self.period = float(tech.spice["feasible_period"])
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feasible_delays = [{} for i in range(self.total_ports)]
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#Get initial feasible delays from first port
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feasible_delays[self.read_ports[0]] = self.find_feasible_period_one_port(self.read_ports[0])
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feasible_delays[self.read_index[0]] = self.find_feasible_period_one_port(self.read_index[0])
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previous_period = self.period
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#Loops through all the ports checks if the feasible period works. Everything restarts it if does not.
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#Write ports do not produce delays which is why they are not included here.
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i = 1
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while i < len(self.read_ports):
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port = self.read_ports[i]
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while i < len(self.read_index):
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port = self.read_index[i]
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#Only extract port values from the specified port, not the entire results.
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feasible_delays[port].update(self.find_feasible_period_one_port(port))
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#Function sets the period. Restart the entire process if period changes to collect accurate delays
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@ -461,7 +419,7 @@ class delay():
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#Sanity Check
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debug.check(self.period > 0, "Target simulation period non-positive")
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result = [{} for i in range(self.total_port_num)]
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result = [{} for i in range(self.total_ports)]
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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@ -563,7 +521,7 @@ class delay():
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#Find the minimum period for all ports. Start at one port and perform binary search then use that delay as a starting position.
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#For testing purposes, only checks read ports.
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for port in self.read_ports:
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for port in self.read_index:
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target_period = self.find_min_period_one_port(feasible_delays, port, lb_period, ub_period, target_period)
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#The min period of one port becomes the new lower bound. Reset the upper_bound.
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lb_period = target_period
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@ -728,8 +686,8 @@ class delay():
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"""Simulate all specified output loads and input slews pairs of all ports"""
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measure_data = self.get_empty_measure_data_dict()
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#Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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self.targ_read_ports = self.read_index
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self.targ_write_ports = self.write_index
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for slew in slews:
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for load in loads:
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self.set_load_slew(load,slew)
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@ -738,7 +696,7 @@ class delay():
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debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(self.slew,self.load))
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debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew,self.load))
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#The results has a dict for every port but dicts can be empty (e.g. ports were not targeted).
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for port in range(self.total_port_num):
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for port in range(self.total_ports):
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for mname,value in delay_results[port].items():
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if "power" in mname:
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# Subtract partial array leakage and add full array leakage for the power measures
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@ -746,119 +704,8 @@ class delay():
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else:
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measure_data[port][mname].append(value)
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return measure_data
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def add_data(self, data, port):
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""" Add the array of data values """
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debug.check(len(data)==self.word_size, "Invalid data word size.")
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debug.check(port < len(self.data_values), "Port number cannot index data values.")
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index = 0
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for c in data:
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if c=="0":
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self.data_values[port][index].append(0)
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elif c=="1":
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self.data_values[port][index].append(1)
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else:
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debug.error("Non-binary data string",1)
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index += 1
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def add_address(self, address, port):
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""" Add the array of address values """
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debug.check(len(address)==self.addr_size, "Invalid address size.")
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index = 0
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for c in address:
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if c=="0":
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self.addr_values[port][index].append(0)
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elif c=="1":
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self.addr_values[port][index].append(1)
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else:
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debug.error("Non-binary address string",1)
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index += 1
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def add_noop_one_port(self, address, data, port):
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""" Add the control values for a noop to a single port. """
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#This is to be used as a helper function for the other add functions. Cycle and comments are omitted.
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self.add_control_one_port(port, "noop")
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if port in self.write_ports:
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self.add_data(data,port)
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self.add_address(address, port)
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def add_noop_all_ports(self, comment, address, data):
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""" Add the control values for a noop to all ports. """
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self.add_comment("All", comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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for port in range(self.total_port_num):
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self.add_noop_one_port(address, data, port)
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def add_read(self, comment, address, data, port):
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""" Add the control values for a read cycle. """
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debug.check(port in self.read_ports, "Cannot add read cycle to a write port.")
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self.add_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "read")
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#If the port is also a readwrite then add data.
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if port in self.write_ports:
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self.add_data(data,port)
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self.add_address(address, port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in range(self.total_port_num):
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_write(self, comment, address, data, port):
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""" Add the control values for a write cycle. """
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debug.check(port in self.write_ports, "Cannot add read cycle to a read port.")
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self.add_comment(port, comment)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_control_one_port(port, "write")
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self.add_data(data,port)
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self.add_address(address,port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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for unselected_port in range(self.total_port_num):
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if unselected_port != port:
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self.add_noop_one_port(address, noop_data, unselected_port)
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def add_control_one_port(self, port, op):
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"""Appends control signals for operation to a given port"""
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#Determine values to write to port
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web_val = 1
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csb_val = 1
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if op == "read":
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csb_val = 0
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elif op == "write":
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csb_val = 0
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web_val = 0
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elif op != "noop":
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debug.error("Could not add control signals for port {0}. Command {1} not recognized".format(port,op),1)
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#Append the values depending on the type of port
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self.csb_values[port].append(csb_val)
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#If port is in both lists, add rw control signal. Condition indicates its a RW port.
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if port in self.write_ports and port in self.read_ports:
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self.web_values[port].append(web_val)
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def add_comment(self, port, comment):
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"""Add comment to list to be printed in stimulus file"""
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#Clean up time before appending. Make spacing dynamic as well.
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time = "{0:.2f} ns:".format(self.t_current)
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time_spacing = len(time)+6
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self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
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port,
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time,
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time_spacing,
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comment))
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def gen_test_cycles_one_port(self, read_port, write_port):
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"""Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge)
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of the cycles to do a timing evaluation of a single port. Current: Values overwritten for multiple calls"""
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@ -925,11 +772,15 @@ class delay():
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def get_available_port(self,get_read_port):
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"""Returns the first accessible read or write port. """
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if get_read_port and len(self.read_ports) > 0:
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return self.read_ports[0]
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elif not get_read_port and len(self.write_ports) > 0:
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return self.write_ports[0]
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if get_read_port and len(self.read_index) > 0:
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return self.read_index[0]
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elif not get_read_port and len(self.write_index) > 0:
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return self.write_index[0]
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return None
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def set_stimulus_variables(self):
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simulation.set_stimulus_variables(self)
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self.measure_cycles = {}
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def create_test_cycles(self):
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"""Returns a list of key time-points [ns] of the waveform (each rising edge)
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@ -937,31 +788,13 @@ class delay():
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and does not need a rising edge."""
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#Using this requires setting at least one port to target for simulation.
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if len(self.targ_write_ports) == 0 and len(self.targ_read_ports) == 0:
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debug.error("No ports selected for characterization.",1)
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# Start at time 0
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self.t_current = 0
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# Cycle times (positive edge) with comment
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self.cycle_comments = []
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self.cycle_times = []
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self.measure_cycles = {}
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# Control signals for ports. These are not the final signals and will likely be changed later.
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#web is the enable for write ports. Dicts used for simplicity as ports are not necessarily incremental.
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self.web_values = {port:[] for port in self.write_ports}
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#csb acts as an enable for the read ports.
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self.csb_values = {port:[] for port in range(self.total_port_num)}
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# Address and data values for each address/data bit. A 3d list of size #ports x bits x cycles.
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self.data_values=[[[] for bit in range(self.word_size)] for port in range(len(self.write_ports))]
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self.addr_values=[[[] for bit in range(self.addr_size)] for port in range(self.total_port_num)]
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debug.error("No port selected for characterization.",1)
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self.set_stimulus_variables()
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#Get any available read/write port in case only a single write or read ports is being characterized.
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_write_port = self.get_available_port(get_read_port=False)
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#These checks should be superceded by check_arguments which should have been called earlier, so this is a double check.
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debug.check(cur_read_port != None, "Characterizer requires at least 1 read port")
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||||
debug.check(cur_write_port != None, "Characterizer requires at least 1 write port")
|
||||
|
||||
|
|
@ -1026,7 +859,7 @@ class delay():
|
|||
|
||||
def gen_data(self):
|
||||
""" Generates the PWL data inputs for a simulation timing test. """
|
||||
for write_port in self.write_ports:
|
||||
for write_port in self.write_index:
|
||||
for i in range(self.word_size):
|
||||
sig_name="{0}{1}_{2} ".format(self.din_name,write_port, i)
|
||||
self.stim.gen_pwl(sig_name, self.cycle_times, self.data_values[write_port][i], self.period, self.slew, 0.05)
|
||||
|
|
@ -1036,16 +869,16 @@ class delay():
|
|||
Generates the address inputs for a simulation timing test.
|
||||
This alternates between all 1's and all 0's for the address.
|
||||
"""
|
||||
for port in range(self.total_port_num):
|
||||
for port in range(self.total_ports):
|
||||
for i in range(self.addr_size):
|
||||
sig_name = "{0}{1}_{2}".format(self.addr_name,port,i)
|
||||
self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][i], self.period, self.slew, 0.05)
|
||||
|
||||
def gen_control(self):
|
||||
""" Generates the control signals """
|
||||
for port in range(self.total_port_num):
|
||||
for port in range(self.total_ports):
|
||||
self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
|
||||
if port in self.read_ports and port in self.write_ports:
|
||||
if port in self.read_index and port in self.write_index:
|
||||
self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
|
||||
|
||||
|
||||
|
|
@ -1053,5 +886,5 @@ class delay():
|
|||
"""Make a dict of lists for each type of delay and power measurement to append results to"""
|
||||
measure_names = self.delay_meas_names + self.power_meas_names
|
||||
#Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists.
|
||||
measure_data = [{mname:[] for mname in measure_names} for i in range(self.total_port_num)]
|
||||
measure_data = [{mname:[] for mname in measure_names} for i in range(self.total_ports)]
|
||||
return measure_data
|
||||
|
|
|
|||
|
|
@ -81,7 +81,6 @@ class simulation():
|
|||
def add_data(self, data, port):
|
||||
""" Add the array of data values """
|
||||
debug.check(len(data)==self.word_size, "Invalid data word size.")
|
||||
#debug.check(port < len(self.data_values), "Port number cannot index data values.")
|
||||
|
||||
bit = self.word_size - 1
|
||||
for c in data:
|
||||
|
|
@ -109,12 +108,9 @@ class simulation():
|
|||
|
||||
def add_write(self, comment, address, data, port):
|
||||
""" Add the control values for a write cycle. """
|
||||
debug.info(1, comment)
|
||||
debug.info(2, comment)
|
||||
debug.check(port in self.write_index, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_index))
|
||||
self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
|
||||
self.t_current,
|
||||
comment,
|
||||
port))
|
||||
self.append_cycle_comment(port, comment)
|
||||
self.cycle_times.append(self.t_current)
|
||||
self.t_current += self.period
|
||||
|
||||
|
|
@ -131,12 +127,9 @@ class simulation():
|
|||
|
||||
def add_read(self, comment, address, data, port):
|
||||
""" Add the control values for a read cycle. """
|
||||
debug.info(1, comment)
|
||||
debug.info(2, comment)
|
||||
debug.check(port in self.read_index, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_index))
|
||||
self.cycle_comments.append("Cycle {0:2d}\tPort {3}\t{1:5.2f}ns:\t{2}".format(len(self.cycle_comments),
|
||||
self.t_current,
|
||||
comment,
|
||||
port))
|
||||
self.append_cycle_comment(port, comment)
|
||||
self.cycle_times.append(self.t_current)
|
||||
self.t_current += self.period
|
||||
self.add_control_one_port(port, "read")
|
||||
|
|
@ -152,13 +145,22 @@ class simulation():
|
|||
for unselected_port in range(self.total_ports):
|
||||
if unselected_port != port:
|
||||
self.add_noop_one_port(address, noop_data, unselected_port)
|
||||
|
||||
def append_cycle_comment(self, port, comment):
|
||||
"""Add comment to list to be printed in stimulus file"""
|
||||
#Clean up time before appending. Make spacing dynamic as well.
|
||||
time = "{0:.2f} ns:".format(self.t_current)
|
||||
time_spacing = len(time)+6
|
||||
self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
|
||||
port,
|
||||
time,
|
||||
time_spacing,
|
||||
comment))
|
||||
|
||||
def add_noop_all_ports(self, comment, address, data):
|
||||
""" Add the control values for a noop to all ports. """
|
||||
debug.info(1, comment)
|
||||
self.cycle_comments.append("Cycle {0:2d}\tPort All\t{1:5.2f}ns:\t{2}".format(len(self.cycle_times),
|
||||
self.t_current,
|
||||
comment))
|
||||
debug.info(2, comment)
|
||||
self.append_cycle_comment("All", comment)
|
||||
self.cycle_times.append(self.t_current)
|
||||
self.t_current += self.period
|
||||
|
||||
|
|
|
|||
|
|
@ -43,8 +43,8 @@ class worst_case(delay):
|
|||
test_bits = self.get_test_bits()
|
||||
bit_delays = self.simulate_for_bit_delays(test_bits)
|
||||
|
||||
for delay in bit_delays:
|
||||
debug.info(1, "{}".format(delay))
|
||||
for i in range(len(test_bits)):
|
||||
debug.info(1, "Bit tested: addr {0[0]} data_pos {0[1]}\n Values {1}".format(test_bits[i], bit_delays[i]))
|
||||
|
||||
def simulate_for_bit_delays(self, test_bits):
|
||||
"""Simulates the delay of the sram of over several bits."""
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@ output_path = "temp"
|
|||
output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
|
||||
|
||||
#Setting for multiport
|
||||
# netlist_only = True
|
||||
# bitcell = "pbitcell"
|
||||
# replica_bitcell="replica_pbitcell"
|
||||
# num_rw_ports = 1
|
||||
# num_r_ports = 1
|
||||
# num_w_ports = 0
|
||||
netlist_only = True
|
||||
bitcell = "pbitcell"
|
||||
replica_bitcell="replica_pbitcell"
|
||||
num_rw_ports = 1
|
||||
num_r_ports = 1
|
||||
num_w_ports = 0
|
||||
|
|
|
|||
|
|
@ -31,14 +31,14 @@ class worst_case_timing_sram_test(openram_test):
|
|||
if not OPTS.spice_exe:
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
word_size, num_words, num_banks = 32, 32, 1
|
||||
word_size, num_words, num_banks = 2, 16, 1
|
||||
from sram import sram
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=word_size,
|
||||
num_words=num_words,
|
||||
num_banks=num_banks)
|
||||
#c.words_per_row=1
|
||||
c.compute_sizes()
|
||||
c.words_per_row=1
|
||||
#c.compute_sizes()
|
||||
debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
|
||||
word_size, num_words, num_banks))
|
||||
s = sram(c, name="sram1")
|
||||
|
|
@ -56,8 +56,10 @@ class worst_case_timing_sram_test(openram_test):
|
|||
sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
|
||||
verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
|
||||
sp_sim_file = sp_pex_file
|
||||
debug.info(1, "Performing spice simulations with backannotated spice file.")
|
||||
else:
|
||||
sp_sim_file = sp_netlist_file
|
||||
debug.info(1, "Performing spice simulations with spice netlist.")
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
|
||||
wc = worst_case(s.s, sp_sim_file, corner)
|
||||
|
|
|
|||
Loading…
Reference in New Issue