mirror of https://github.com/VLSIDA/OpenRAM.git
Clean up psingle_bank_test
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@ -29,27 +29,33 @@ class psingle_bank_test(openram_test):
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OPTS.num_r_ports = 0
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c = sram_config(word_size=4,
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num_words=16)
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c.words_per_row=1
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debug.info(1, "No column mux")
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a = bank(c, name="bank1_1rw_0w_0r_single")
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name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
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a = bank(c, name=name)
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self.local_check(a)
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c.num_words=32
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c.words_per_row=2
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debug.info(1, "Two way column mux")
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a = bank(c, name="bank1_1rw_0w_0r_single")
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name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
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a = bank(c, name=name)
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self.local_check(a)
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c.num_words=64
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c.words_per_row=4
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debug.info(1, "Four way column mux")
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a = bank(c, name="bank1_1rw_0w_0r_single")
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name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
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a = bank(c, name=name)
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self.local_check(a)
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c.word_size=2
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c.num_words=128
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c.words_per_row=8
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debug.info(1, "Four way column mux")
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a = bank(c, name="bank1_1rw_0w_0r_single")
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name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
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a = bank(c, name=name)
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self.local_check(a)
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@ -38,7 +38,6 @@ class single_bank_test(openram_test):
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a = bank(c, name="bank3_single")
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self.local_check(a)
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# Eight way has a short circuit of one column mux select to gnd rail
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c.word_size=2
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c.num_words=128
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c.words_per_row=8
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