mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes.
This commit is contained in:
Hunter Nichols
parent
016604f846
commit
da1b003d10
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@ -17,7 +17,8 @@ class lib:
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self.sram = sram
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self.sp_file = sp_file
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self.use_model = use_model
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self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
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#self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
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self.set_port_indices()
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self.prepare_tables()
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@ -25,7 +26,10 @@ class lib:
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self.characterize_corners()
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def set_port_indices(self):
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self.total_port_num = self.sram.total_ports
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self.read_ports = self.sram.read_index
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self.write_ports = self.sram.write_index
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def gen_port_names(self):
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"""Generates the port names to be written to the lib file"""
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@ -339,7 +343,6 @@ class lib:
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self.lib.write(" pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port))
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self.write_FF_setuphold(read_port)
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port))
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@ -361,7 +364,7 @@ class lib:
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self.lib.write(" }\n\n") # bus
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def write_data_bus_input(self, write_port):
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""" Adds data bus timing results."""
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""" Adds DIN data bus timing results."""
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self.lib.write(" bus(DIN{0}){{\n".format(write_port))
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self.lib.write(" bus_type : DATA; \n")
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@ -371,8 +374,11 @@ class lib:
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self.lib.write(" memory_write(){ \n")
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self.lib.write(" address : ADDR{0}; \n".format(write_port))
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self.lib.write(" clocked_on : clk{0}; \n".format(write_port))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" pin(DIN{1}[{0}:0]){{\n".format(self.sram.word_size - 1, write_port))
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self.write_FF_setuphold(write_port)
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self.lib.write(" }\n") # pin
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self.lib.write(" }\n") #bus
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def write_data_bus(self, port):
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""" Adds data bus timing results."""
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@ -14,5 +14,5 @@ netlist_only = True
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bitcell = "pbitcell"
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replica_bitcell="replica_pbitcell"
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num_rw_ports = 1
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num_r_ports = 0
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num_r_ports = 1
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num_w_ports = 1
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@ -78,214 +78,216 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 948.52275;
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area : 977.4951374999999;
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leakage_power () {
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when : "CSb";
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value : 0.0021292;
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when : "CSb0";
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value : 0.0011164579999999999;
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}
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cell_leakage_power : 0;
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bus(DIN){
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bus(DIN0){
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bus_type : DATA;
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direction : input;
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capacitance : 0.2091;
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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address : ADDR0;
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clocked_on : clk0;
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}
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pin(DIN0[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016");
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}
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}
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}
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}
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bus(DOUT){
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bus(DOUT0){
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bus_type : DATA;
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direction : output;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR;
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}
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pin(DOUT[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016");
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}
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address : ADDR0;
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}
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pin(DOUT0[1:0]){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk";
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related_pin : "clk0";
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timing_type : rising_edge;
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cell_rise(CELL_TABLE) {
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values("0.229, 0.23, 0.234",\
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"0.23, 0.23, 0.234",\
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"0.236, 0.236, 0.24");
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values("0.235, 0.235, 0.239",\
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"0.235, 0.236, 0.24",\
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"0.241, 0.242, 0.246");
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}
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cell_fall(CELL_TABLE) {
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values("2.555, 2.556, 2.568",\
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"2.555, 2.557, 2.569",\
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"2.562, 2.563, 2.575");
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values("2.583, 2.585, 2.612",\
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"2.584, 2.585, 2.613",\
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"2.59, 2.592, 2.62");
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}
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rise_transition(CELL_TABLE) {
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values("0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028",\
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"0.02, 0.021, 0.028");
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values("0.022, 0.022, 0.03",\
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"0.022, 0.023, 0.03",\
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"0.022, 0.022, 0.03");
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}
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fall_transition(CELL_TABLE) {
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values("0.111, 0.112, 0.115",\
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"0.111, 0.111, 0.115",\
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"0.111, 0.111, 0.116");
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values("0.078, 0.079, 0.083",\
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"0.078, 0.079, 0.083",\
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"0.079, 0.079, 0.083");
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}
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}
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}
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}
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bus(ADDR){
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bus(ADDR0){
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bus_type : ADDR;
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direction : input;
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capacitance : 0.2091;
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max_transition : 0.04;
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pin(ADDR[3:0]){
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pin(ADDR0[3:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027");
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values("0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015");
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values("0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004");
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values("-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016");
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values("-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016");
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}
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}
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}
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}
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pin(CSb){
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pin(CSb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027");
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values("0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015");
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values("0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004");
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values("-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016");
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values("-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016");
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}
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}
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}
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pin(WEb){
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pin(WEb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027",\
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"0.009, 0.015, 0.027");
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values("0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039",\
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"0.033, 0.033, 0.039");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015",\
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"0.009, 0.009, 0.015");
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values("0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033",\
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"0.027, 0.027, 0.033");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk";
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004",\
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"0.002, 0.002, -0.004");
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values("-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022",\
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"-0.01, -0.016, -0.022");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016",\
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"-0.004, -0.004, -0.016");
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values("-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016",\
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"-0.016, -0.016, -0.016");
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}
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}
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}
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pin(clk){
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pin(clk0){
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clock : true;
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb & clk & !WEb";
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when : "!CSb0 & clk0 & !WEb0";
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rise_power(scalar){
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values("0.027431397222222223");
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values("0.03599689694444445");
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}
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fall_power(scalar){
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values("0.027431397222222223");
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values("0.03599689694444445");
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}
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}
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internal_power(){
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when : "!CSb & !clk & WEb";
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when : "!CSb0 & !clk0 & WEb0";
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rise_power(scalar){
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values("0.026240397222222222");
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values("0.029906643888888886");
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}
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fall_power(scalar){
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values("0.026240397222222222");
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values("0.029906643888888886");
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}
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}
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internal_power(){
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when : "CSb";
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when : "CSb0";
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rise_power(scalar){
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values("0");
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}
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@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
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}
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timing(){
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timing_type :"min_pulse_width";
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related_pin : clk;
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related_pin : clk0;
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rise_constraint(scalar) {
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values("2.422");
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}
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@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk;
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related_pin : clk0;
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rise_constraint(scalar) {
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values("4.844");
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}
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@ -78,96 +78,98 @@ cell (sram_2_16_1_freepdk45){
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 948.52275;
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area : 977.4951374999999;
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leakage_power () {
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when : "CSb";
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value : 0.000168;
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when : "CSb0";
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value : 0.000179;
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}
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cell_leakage_power : 0;
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bus(DIN){
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bus(DIN0){
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bus_type : DATA;
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direction : input;
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capacitance : 0.2091;
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memory_write(){
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address : ADDR;
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clocked_on : clk;
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address : ADDR0;
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clocked_on : clk0;
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}
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pin(DIN0[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT){
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
values("0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113",\
|
||||
"0.103, 0.104, 0.113");
|
||||
values("0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098",\
|
||||
"0.098, 0.098, 0.098");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018",\
|
||||
"0.006, 0.007, 0.018");
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR[3:0]){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -181,7 +183,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -196,12 +198,12 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -215,7 +217,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -229,12 +231,12 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -248,7 +250,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -262,30 +264,30 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.0739870044551111");
|
||||
values("0.0747594982142222");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb";
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
|
@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
|
|
@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -78,214 +78,216 @@ cell (sram_2_16_1_freepdk45){
|
|||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 948.52275;
|
||||
area : 977.4951374999999;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb";
|
||||
value : 0.0021292;
|
||||
when : "CSb0";
|
||||
value : 0.0011164579999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN){
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR;
|
||||
clocked_on : clk;
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT){
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR;
|
||||
}
|
||||
pin(DOUT[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
}
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.227, 0.227, 0.231",\
|
||||
"0.227, 0.228, 0.232",\
|
||||
"0.233, 0.234, 0.238");
|
||||
values("0.233, 0.233, 0.237",\
|
||||
"0.233, 0.234, 0.237",\
|
||||
"0.239, 0.24, 0.244");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("2.555, 2.557, 2.569",\
|
||||
"2.556, 2.557, 2.569",\
|
||||
"2.562, 2.563, 2.576");
|
||||
values("2.584, 2.585, 2.611",\
|
||||
"2.584, 2.585, 2.612",\
|
||||
"2.591, 2.592, 2.618");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028",\
|
||||
"0.02, 0.021, 0.028");
|
||||
values("0.022, 0.022, 0.03",\
|
||||
"0.022, 0.023, 0.03",\
|
||||
"0.022, 0.023, 0.03");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.11, 0.11, 0.114",\
|
||||
"0.109, 0.11, 0.113",\
|
||||
"0.11, 0.11, 0.114");
|
||||
values("0.076, 0.077, 0.082",\
|
||||
"0.077, 0.077, 0.082",\
|
||||
"0.077, 0.077, 0.082");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR){
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR[3:0]){
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb){
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb){
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027",\
|
||||
"0.009, 0.015, 0.027");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015",\
|
||||
"0.009, 0.009, 0.015");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004",\
|
||||
"0.002, 0.002, -0.004");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016",\
|
||||
"-0.004, -0.004, -0.016");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb & clk & !WEb";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.025181683333333333");
|
||||
values("0.03334771594444444");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.025181683333333333");
|
||||
values("0.03334771594444444");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb & !clk & WEb";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.024945991666666667");
|
||||
values("0.028457026222222223");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.024945991666666667");
|
||||
values("0.028457026222222223");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb";
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
|
|
@ -295,7 +297,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("2.422");
|
||||
}
|
||||
|
|
@ -305,7 +307,7 @@ cell (sram_2_16_1_freepdk45){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("4.844");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -78,11 +78,11 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000175;
|
||||
value : 0.0009813788999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
|
|
@ -91,7 +91,37 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
|
|
@ -103,57 +133,29 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
values("1.556, 1.576, 1.751",\
|
||||
"1.559, 1.579, 1.754",\
|
||||
"1.624, 1.643, 1.819");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
values("3.445, 3.504, 3.926",\
|
||||
"3.448, 3.507, 3.93",\
|
||||
"3.49, 3.549, 3.972");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
values("0.13, 0.169, 0.574",\
|
||||
"0.13, 0.169, 0.574",\
|
||||
"0.13, 0.169, 0.574");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
values("0.467, 0.49, 0.959",\
|
||||
"0.467, 0.49, 0.959",\
|
||||
"0.47, 0.493, 0.96");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -167,30 +169,30 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -201,30 +203,30 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -234,54 +236,54 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228",\
|
||||
"0.167, 0.167, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
values("0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137",\
|
||||
"0.131, 0.125, 0.137");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
values("-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089",\
|
||||
"-0.089, -0.089, -0.089");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("9.972790277777777");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("9.972790277777777");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("8.899322499999998");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("8.899322499999998");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
|
|
@ -295,22 +297,22 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("2.344");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
values("2.344");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
values("4.688");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0");
|
||||
values("4.688");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -78,11 +78,11 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 60774.3;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000175;
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
|
|
@ -91,21 +91,12 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -119,7 +110,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -131,9 +122,20 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
|
|
@ -167,7 +169,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -181,7 +183,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -201,7 +203,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -215,7 +217,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -234,7 +236,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
|
|
@ -248,7 +250,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
|
|
@ -262,26 +264,26 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("11.3007276371");
|
||||
values("11.3049604371");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
|
|
@ -295,7 +297,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
|
|
@ -305,7 +307,7 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
||||
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
|
|
@ -9,7 +9,7 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
|||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 5.0 ;
|
||||
voltage : 1.0 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
|
|
@ -22,7 +22,7 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
|||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_voltage : 1.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
|
|
@ -38,15 +38,15 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
|||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.052275, 0.2091, 1.6728");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.00125, 0.005, 0.04");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
|
@ -68,7 +68,7 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
|
|||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_scn4m_subm){
|
||||
cell (sram_2_16_1_freepdk45){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
|
|
@ -78,82 +78,84 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 60176.520000000004;
|
||||
area : 977.4951374999999;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.025716199999999998;
|
||||
value : 0.0011164579999999999;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("1.277, 1.297, 1.475",\
|
||||
"1.28, 1.3, 1.479",\
|
||||
"1.347, 1.367, 1.545");
|
||||
values("0.235, 0.235, 0.239",\
|
||||
"0.235, 0.236, 0.24",\
|
||||
"0.241, 0.242, 0.246");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("3.217, 3.281, 3.71",\
|
||||
"3.22, 3.285, 3.714",\
|
||||
"3.261, 3.325, 3.75");
|
||||
values("2.583, 2.585, 2.612",\
|
||||
"2.584, 2.585, 2.613",\
|
||||
"2.59, 2.592, 2.62");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.122, 0.164, 0.579",\
|
||||
"0.122, 0.164, 0.578",\
|
||||
"0.122, 0.164, 0.58");
|
||||
values("0.022, 0.022, 0.03",\
|
||||
"0.022, 0.023, 0.03",\
|
||||
"0.022, 0.022, 0.03");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.363, 0.396, 0.958",\
|
||||
"0.363, 0.396, 0.957",\
|
||||
"0.366, 0.399, 0.951");
|
||||
values("0.078, 0.079, 0.083",\
|
||||
"0.078, 0.079, 0.083",\
|
||||
"0.079, 0.079, 0.083");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -162,35 +164,35 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -198,90 +200,90 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228",\
|
||||
"0.179, 0.173, 0.228");
|
||||
values("0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039",\
|
||||
"0.033, 0.033, 0.039");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143",\
|
||||
"0.125, 0.125, 0.143");
|
||||
values("0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033",\
|
||||
"0.027, 0.027, 0.033");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk";
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114",\
|
||||
"-0.065, -0.071, -0.114");
|
||||
values("-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022",\
|
||||
"-0.01, -0.016, -0.022");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095",\
|
||||
"-0.089, -0.089, -0.095");
|
||||
values("-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016",\
|
||||
"-0.016, -0.016, -0.016");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk){
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk & !WEb0";
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("9.141838916666668");
|
||||
values("0.03599689694444445");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("9.141838916666668");
|
||||
values("0.03599689694444445");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk & WEb0";
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("8.304491694444444");
|
||||
values("0.029906643888888886");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("8.304491694444444");
|
||||
values("0.029906643888888886");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
|
|
@ -295,22 +297,22 @@ cell (sram_2_16_1_scn4m_subm){
|
|||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("2.344");
|
||||
values("2.422");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("2.344");
|
||||
values("2.422");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk;
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("4.688");
|
||||
values("4.844");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("4.688");
|
||||
values("4.844");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue