Merge branch 'dev' into supply_routing

CONTRIBUTING.md

@@ -20,7 +20,7 @@ other OpenRAM features. Please see the README.md file on how to run
 the unit tests. Unit tests should work in all technologies. We will run
 the tests on your contributions before they will be accepted.
 
-# Internally Development
+# Internal Development
 
 For internal development, follow all of the following steps EXCEPT
 do not fork your own copy. Instead, create a branch in our private repository
@@ -32,21 +32,21 @@ All unit tests should pass first.
 1. One time, create a GitHub account at http://github.com
 
 2. Create a fork of the OpenRAM project on the github web page:
-   https://github.com/mguthaus/OpenRAM
+   https://github.com/vlsida/openram
    It is on the upper right and says "Fork": This will make your own
    OpenRAM repository on GitHub in your account.
 
 3. Clone your repository (or use an existing cloned copy if you've
    already done this once):
 ```
-  git clone https://github.com/<youruser>/OpenRAM.git
-  cd OpenRAM
+  git clone https://github.com/<youruser>/oepnram.git
+  cd openram
 ```
 
 4. Set up a new upstream that points to MY OpenRAM repository that you
    forked (only first time):
 ```
-   git remote add upstream https://github.com/mguthaus/OpenRAM.git
+   git remote add upstream https://github.com/vlsida/openram.git
 ```
    You now have two remotes for this project:
    * origin which points to your GitHub fork of the project. You can read

compiler/example_config_freepdk45.py

@@ -9,10 +9,3 @@ temperatures = [25]
 output_path = "temp"
 output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
-#Setting for multiport
-# netlist_only = True
-# bitcell = "pbitcell"
-# replica_bitcell="replica_pbitcell"
-# num_rw_ports = 1
-# num_r_ports = 0
-# num_w_ports = 1

compiler/example_config_scn4m_subm.py

@@ -3,16 +3,9 @@ num_words = 16
 
 tech_name = "scn4m_subm"
 process_corners = ["TT"]
-supply_voltages = [ 5.0 ]
+supply_voltages = [ 3.3 ]
 temperatures = [ 25 ]
 
 output_path = "temp"
 output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
 
-#Setting for multiport
-netlist_only = True
-bitcell = "pbitcell"
-replica_bitcell="replica_pbitcell"
-num_rw_ports = 1
-num_r_ports = 1
-num_w_ports = 1