mirror of https://github.com/VLSIDA/OpenRAM.git
Remove cell rename during DRC. Keep flatten.
This commit is contained in:
parent
ee05865919
commit
7ead566154
|
|
@ -43,9 +43,9 @@ def write_magic_script(cell_name, gds_name, extract=False):
|
|||
# (e.g. with routes)
|
||||
f.write("flatten {}_new\n".format(cell_name))
|
||||
f.write("load {}_new\n".format(cell_name))
|
||||
f.write("cellname rename {0}_new {0}\n".format(cell_name))
|
||||
f.write("load {}\n".format(cell_name))
|
||||
f.write("writeall force\n")
|
||||
#f.write("cellname rename {0}_new {0}\n".format(cell_name))
|
||||
#f.write("load {}\n".format(cell_name))
|
||||
f.write("writeall force {0}_new\n".format(cell_name))
|
||||
f.write("drc check\n")
|
||||
f.write("drc catchup\n")
|
||||
f.write("drc count total\n")
|
||||
|
|
|
|||
Loading…
Reference in New Issue