mirror of https://github.com/VLSIDA/OpenRAM.git
Improved debug comments for functional test
This commit is contained in:
Michael Timothy Grimes
parent
1a0568f244
commit
2053a1ca4d
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@ -56,14 +56,14 @@ class functional(simulation):
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check = 0
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# First cycle idle
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self.add_noop_all_ports("Idle at time {0}n".format(self.t_current),
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"0"*self.addr_size, "0"*self.word_size)
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debug_comment = self.cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current)
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self.add_noop_all_ports(debug_comment, "0"*self.addr_size, "0"*self.word_size)
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# Write at least once
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addr = self.gen_addr()
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word = self.gen_data()
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self.add_write("Writing {0} to address {1} (from port {2}) at time {3}n".format(word, addr, 0, self.t_current),
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addr, word, 0)
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debug_comment = self.cycle_comment("write", word, addr, 0, self.t_current)
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self.add_write(debug_comment, addr, word, 0)
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self.stored_words[addr] = word
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# Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously.
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@ -72,8 +72,8 @@ class functional(simulation):
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if self.port_id[port] == "w":
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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self.add_read_one_port("Reading {0} from address {1} (from port {2}) at time {3}n".format(word, addr, port, self.t_current),
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addr, rw_read_data, port)
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debug_comment = self.cycle_comment("read", word, addr, port, self.t_current)
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self.add_read_one_port(debug_comment, addr, rw_read_data, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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self.cycle_times.append(self.t_current)
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@ -101,8 +101,8 @@ class functional(simulation):
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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self.add_write_one_port("Writing {0} to address {1} (from port {2}) at time {3}n".format(word, addr, port, self.t_current),
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addr, word, port)
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debug_comment = self.cycle_comment("write", word, addr, port, self.t_current)
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self.add_write_one_port(debug_comment, addr, word, port)
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self.stored_words[addr] = word
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w_addrs.append(addr)
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else:
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@ -111,8 +111,8 @@ class functional(simulation):
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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self.add_read_one_port("Reading {0} from address {1} (from port {2}) at time {3}n".format(word, addr, port, self.t_current),
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addr, rw_read_data, port)
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debug_comment = self.cycle_comment("read", word, addr, port, self.t_current)
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self.add_read_one_port(debug_comment, addr, rw_read_data, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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@ -120,8 +120,8 @@ class functional(simulation):
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self.t_current += self.period
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# Last cycle idle needed to correctly measure the value on the second to last clock edge
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self.add_noop_all_ports("Idle at time {0}n".format(self.t_current),
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"0"*self.addr_size, "0"*self.word_size)
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debug_comment = self.cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current)
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self.add_noop_all_ports(debug_comment, "0"*self.addr_size, "0"*self.word_size)
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def read_stim_results(self):
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# Extrat DOUT values from spice timing.lis
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@ -148,10 +148,11 @@ class functional(simulation):
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def check_stim_results(self):
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for i in range(len(self.write_check)):
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if self.write_check[i][0] != self.read_check[i][0]:
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error = "FAILED: {0} value {1} does not match written value {2} read at time {3}n".format(self.read_check[i][1],
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self.read_check[i][0],
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self.write_check[i][0],
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self.read_check[i][2])
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error = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n".format(self.read_check[i][1],
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self.read_check[i][0],
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self.write_check[i][0],
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int((self.read_check[i][2]-self.period)/self.period),
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self.read_check[i][2])
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return(0, error)
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return(1, "SUCCESS")
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@ -197,4 +197,25 @@ class simulation():
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if port in self.write_index:
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self.add_data(data,port)
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self.add_address(address, port)
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def cycle_comment(self, op, word, addr, port, t_current):
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if op == "noop":
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comment = "\tIdle during cycle {0} ({1}ns - {2}ns)".format(int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "write":
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comment = "\tWriting {0} to address {1} (from port {2}) during cylce {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cylce {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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return comment
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