luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Adding mutliport constants to design.py to reduce the need for copied code across multiple modules.

This commit is contained in:
Michael Timothy Grimes 2018-09-28 00:11:39 -07:00
parent 66933ed922
commit a71486e22f
4 changed files with 29 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
compiler/base/design.py
View File

@ -18,6 +18,7 @@ class design(hierarchy_design):
hierarchy_design.__init__(self,name)
self.setup_drc_constants()
self.setup_multiport_constants()
self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
@ -45,7 +46,34 @@ class design(hierarchy_design):
self.contact_to_gate = drc["contact_to_gate"]
self.well_enclose_active = drc["well_enclosure_active"]
self.implant_enclose_active = drc["implant_enclosure_active"]
self.implant_space = drc["implant_to_implant"]
self.implant_space = drc["implant_to_implant"]
def setup_multiport_constants(self):
""" These are contants and lists that aid multiport design """
self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
# Port indices used for data, address, and control signals
# Port IDs used to identify port type
self.write_index = []
self.read_index = []
self.port_id = []
port_number = 0
for port in range(OPTS.num_rw_ports):
self.write_index.append("{}".format(port_number))
self.read_index.append("{}".format(port_number))
self.port_id.append("rw")
port_number += 1
for port in range(OPTS.num_w_ports):
self.write_index.append("{}".format(port_number))
self.port_id.append("w")
port_number += 1
for port in range(OPTS.num_r_ports):
self.read_index.append("{}".format(port_number))
self.port_id.append("r")
port_number += 1
def analytical_power(self, proc, vdd, temp, load):
""" Get total power of a module """

19
compiler/modules/bank.py
View File

@ -29,10 +29,6 @@ class bank(design.design):
design.design.__init__(self, name)
debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words))
self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
# The local control signals are gated when we have bank select logic,
# so this prefix will be added to all of the input signals to create
@ -69,21 +65,6 @@ class bank(design.design):
def add_pins(self):
self.read_index = []
self.port_id = []
port_number = 0
for port in range(OPTS.num_rw_ports):
self.read_index.append("{}".format(port_number))
self.port_id.append("rw")
port_number += 1
for port in range(OPTS.num_w_ports):
self.port_id.append("w")
port_number += 1
for port in range(OPTS.num_r_ports):
self.read_index.append("{}".format(port_number))
self.port_id.append("r")
port_number += 1
""" Adding pins for Bank module"""
for port in range(self.total_read):
for bit in range(self.word_size):

2
compiler/modules/replica_bitline.py
View File

@ -108,8 +108,6 @@ class replica_bitline(design.design):
def create_modules(self):
""" Create all of the module instances in the logical netlist """
self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
# This is the threshold detect inverter on the output of the RBL
self.rbl_inv_inst=self.add_inst(name="rbl_inv",
mod=self.inv)

19
compiler/sram_base.py
View File

@ -19,30 +19,11 @@ class sram_base(design):
self.sram_config = sram_config
sram_config.set_local_config(self)
self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
self.bank_insts = []
def add_pins(self):
""" Add pins for entire SRAM. """
self.read_index = []
self.port_id = []
port_number = 0
for port in range(OPTS.num_rw_ports):
self.read_index.append("{}".format(port_number))
self.port_id.append("rw")
port_number += 1
for port in range(OPTS.num_w_ports):
self.port_id.append("w")
port_number += 1
for port in range(OPTS.num_r_ports):
self.read_index.append("{}".format(port_number))
self.port_id.append("r")
port_number += 1
for port in range(self.total_write):
for bit in range(self.word_size):
self.add_pin("DIN{0}[{1}]".format(port,bit),"INPUT")