mirror of https://github.com/VLSIDA/OpenRAM.git
Move bitcells to their own directory in preparation for custom multiport cells.
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@ -281,7 +281,7 @@ def setup_paths():
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# Add all of the subdirs to the python path
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# These subdirs are modules and don't need to be added: characterizer, verify
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for subdir in ["gdsMill", "tests", "modules", "base", "pgates"]:
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for subdir in ["gdsMill", "tests", "modules", "base", "pgates", "bitcells"]:
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full_path = "{0}/{1}".format(OPENRAM_HOME,subdir)
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debug.check(os.path.isdir(full_path),
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"$OPENRAM_HOME/{0} does not exist: {1}".format(subdir,full_path))
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