mirror of https://github.com/VLSIDA/OpenRAM.git
Allow contains to contain copy. Add connectors when pin doesn't overlap grids.
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7099ee76e9
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@ -120,10 +120,14 @@ class pin_layout:
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def contains(self, other):
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""" Check if a shape contains another rectangle """
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# If it is the same shape entirely, it is contained!
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if self == other:
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return True
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# Can only overlap on the same layer
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if self.layer != other.layer:
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return False
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(ll,ur) = self.rect
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(oll,our) = other.rect
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@ -187,18 +187,17 @@ class pin_group:
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return p
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def find_smallest_connector(self, enclosure_list):
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def find_smallest_connector(self, pin_list, shape_list):
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"""
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Compute all of the connectors between non-overlapping pins and enclosures.
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Compute all of the connectors between the overlapping pins and enclosure shape list..
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Return the smallest.
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"""
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smallest = None
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for pin_list in self.pins:
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for pin in pin_list:
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for enclosure in enclosure_list:
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new_enclosure = self.compute_connector(pin, enclosure)
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if smallest == None or new_enclosure.area()<smallest.area():
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smallest = new_enclosure
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for pin in pin_list:
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for enclosure in shape_list:
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new_enclosure = self.compute_connector(pin, enclosure)
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if smallest == None or new_enclosure.area()<smallest.area():
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smallest = new_enclosure
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return smallest
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@ -316,22 +315,13 @@ class pin_group:
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# Compute the enclosure pin_layout list of the set of tracks
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self.enclosures = self.compute_enclosures()
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# A single set of connected pins is easy, so use the optimized set
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# if len(self.pins)==1:
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# enclosure_list = self.enclosures
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# smallest = self.find_smallest_overlapping(self.pins[0],enclosure_list)
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# if smallest:
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# self.enclosures=[smallest]
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# Save the list of all grids
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#self.all_grids = self.grids.copy()
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# Now, make sure each pin touches an enclosure. If not, add a connector.
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for pin_list in self.pins:
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if not self.overlap_any_shape(pin_list, self.enclosures):
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connector = self.find_smallest_connector(pin_list, self.enclosures)
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debug.check(connector!=None, "Could not find a connector for {} with {}".format(pin_list, self.enclosures))
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self.enclosures.append(connector)
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# Remove the grids that are not covered by the enclosures
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# FIXME: We could probably just store what grids each enclosure overlaps when
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# it was created.
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#for enclosure in self.enclosures:
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# enclosure_in_tracks=router.convert_pin_to_tracks(self.name, enclosure)
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# self.grids.difference_update(enclosure_in_tracks)
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debug.info(3,"Computed enclosure(s) {0}\n {1}\n {2}\n {3}".format(self.name,
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self.pins,
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@ -197,7 +197,7 @@ class router(router_tech):
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combined = pin_group(pin_name, [], self)
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combined.combine_pins(pg1, pg2)
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debug.info(2,"Combining {0} {1} {2}:".format(pin_name, index1, index2))
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debug.info(2, " {0}\n {1}".format(pg1.pins, pg2.pins))
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debug.info(2, "\n {0}\n {1}".format(pg1.pins, pg2.pins))
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debug.info(2," --> {0}\n {1}".format(combined.pins,combined.grids))
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remove_indices.update([index1,index2])
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pin_groups.append(combined)
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@ -91,7 +91,7 @@ class supply_router(router):
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self.route_simple_overlaps(vdd_name)
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self.route_simple_overlaps(gnd_name)
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self.write_debug_gds("debug_simple_route.gds",stop_program=False)
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#self.write_debug_gds("debug_simple_route.gds",stop_program=False)
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# Route the supply pins to the supply rails
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# Route vdd first since we want it to be shorter
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