mirror of https://github.com/VLSIDA/OpenRAM.git
Fix offset of column decoder with new mirroring
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43472dfa46
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68ac7e5955
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@ -233,8 +233,8 @@ class bank(design.design):
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self.row_decoder_offsets[port] = vector(-x_offset,0)
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# LOWER LEFT QUADRANT
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# Place the col decoder right aligned with row decoder (x_offset doesn't change)
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# Below the bitcell array
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# Place the col decoder left aligned with row decoder (x_offset doesn't change)
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# Below the bitcell array with well spacing
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if self.col_addr_size > 0:
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y_offset = self.column_decoder.height
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else:
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@ -291,8 +291,11 @@ class bank(design.design):
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# UPPER RIGHT QUADRANT
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# Place the col decoder right aligned with row decoder (x_offset doesn't change)
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# Below the bitcell array
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y_offset = self.bitcell_array.height + self.m2_gap
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# Above the bitcell array with a well spacing
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if self.col_addr_size > 0:
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y_offset = self.bitcell_array.height + self.column_decoder.height
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else:
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y_offset = self.bitcell_array.height
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y_offset += 2*drc("well_to_well")
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self.column_decoder_offsets[port] = vector(x_offset,y_offset)
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