mirror of https://github.com/VLSIDA/OpenRAM.git
Remove debug statements.
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@ -127,7 +127,6 @@ class pin_group:
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ymax = max(plc.y,elc.y)
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ll = vector(plc.x, ymin)
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ur = vector(prc.x, ymax)
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print(pin,enclosure,ll,ur)
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p = pin_layout(pin.name, [ll, ur], pin.layer)
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elif pin.yoverlaps(enclosure):
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# Is it horizontal overlap, extend pin shape to enclosure
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@ -71,7 +71,7 @@ class supply_router(router):
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# Get the pin shapes
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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#self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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# Add the supply rails in a mesh network and connect H/V with vias
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# Block everything
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