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Merge branch 'multiport' into supply_routing

This commit is contained in:
Matt Guthaus 2018-10-11 10:37:10 -07:00
parent e759c9350b f7d1df6ca7
commit 1333329dd4
1 changed files with 5 additions and 5 deletions
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10
compiler/characterizer/trim_spice.py
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@ -55,8 +55,8 @@ class trim_spice():
else:
col_address = 0
# 1. Keep cells in the bitcell array based on WL and BL
wl_name = "wl[{}]".format(wl_address)
bl_name = "bl[{}]".format(int(self.words_per_row*data_bit + col_address))
wl_name = "wl_{}".format(wl_address)
bl_name = "bl_{}".format(int(self.words_per_row*data_bit + col_address))
# Prepend info about the trimming
addr_msg = "Keeping {} address".format(address)
@ -75,8 +75,8 @@ class trim_spice():
self.sp_buffer.insert(0, "* WARNING: This is a TRIMMED NETLIST.")
wl_regex = r"wl\d*\[{}\]".format(wl_address)
bl_regex = r"bl\d*\[{}\]".format(int(self.words_per_row*data_bit + col_address))
wl_regex = r"wl\d*_{}".format(wl_address)
bl_regex = r"bl\d*_{}".format(int(self.words_per_row*data_bit + col_address))
self.remove_insts("bitcell_array",[wl_regex,bl_regex])
# 2. Keep sense amps basd on BL
@ -87,7 +87,7 @@ class trim_spice():
self.remove_insts("column_mux_array",[bl_regex])
# 4. Keep write driver based on DATA
data_regex = r"data\[{}\]".format(data_bit)
data_regex = r"data_{}".format(data_bit)
self.remove_insts("write_driver_array",[data_regex])
# 5. Keep wordline driver based on WL