mirror of https://github.com/VLSIDA/OpenRAM.git
Only check number of ports when doing layout.
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@ -31,8 +31,6 @@ class bank(design.design):
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design.design.__init__(self, name)
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debug.info(2, "create sram of size {0} with {1} words".format(self.word_size,self.num_words))
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debug.check(len(self.all_ports)<=2,"Bank cannot handle more than two ports.")
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# The local control signals are gated when we have bank select logic,
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# so this prefix will be added to all of the input signals to create
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# the internal gated signals.
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@ -43,6 +41,7 @@ class bank(design.design):
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self.create_netlist()
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if not OPTS.netlist_only:
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debug.check(len(self.all_ports)<=2,"Bank layout cannot handle more than two ports.")
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self.create_layout()
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