mirror of https://github.com/VLSIDA/OpenRAM.git
Adjust ptx positions in precharge to be under the bl rail
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@ -110,11 +110,13 @@ class precharge(pgate.pgate):
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# Compute the other pmos2 location, but determining offset to overlap the
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# source and drain pins
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self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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# This is how much the contact is placed inside the ptx active
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contact_xdiff = self.pmos.get_pin("S").lx()
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# adds the lower pmos to layout
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#base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
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self.lower_pmos_position = vector(max(self.bitcell.get_pin(self.bitcell_bl).lx(), self.well_enclose_active),
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bl_xoffset = self.bitcell.get_pin(self.bitcell_bl).lx()
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self.lower_pmos_position = vector(max(bl_xoffset - contact_xdiff, self.well_enclose_active),
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self.pmos.active_offset.y)
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self.lower_pmos_inst.place(self.lower_pmos_position)
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@ -123,7 +125,7 @@ class precharge(pgate.pgate):
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self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff)
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self.upper_pmos1_inst.place(self.upper_pmos1_pos)
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upper_pmos2_pos = self.upper_pmos1_pos + self.overlap_offset
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upper_pmos2_pos = self.upper_pmos1_pos + overlap_offset
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self.upper_pmos2_inst.place(upper_pmos2_pos)
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def connect_poly(self):
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