Change default col mux size to 2. Add some comments.

This commit is contained in:
Matt Guthaus 2018-11-07 15:43:08 -08:00
parent ad7fe1be51
commit 3d2abc0873
2 changed files with 8 additions and 6 deletions

View File

@ -61,8 +61,7 @@ class single_level_column_mux_array(design.design):
def add_modules(self):
# FIXME: Why is this 8x?
self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
self.mux = single_level_column_mux(bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
self.add_mod(self.mux)

View File

@ -9,13 +9,16 @@ from globals import OPTS
class single_level_column_mux(design.design):
"""
This module implements the columnmux bitline cell used in the design.
Creates a single columnmux cell.
Creates a single columnmux cell with the given integer size relative
to minimum size. Default is 2x.
"""
# This is needed for different bitline spacings
unique_id = 1
def __init__(self, tx_size, bitcell_bl="bl", bitcell_br="br"):
name="single_level_column_mux_{}_no{}".format(tx_size,single_level_column_mux.unique_id)
def __init__(self, tx_size=2, bitcell_bl="bl", bitcell_br="br"):
self.tx_size = int(tx_size)
name="single_level_column_mux_{}_{}".format(self.tx_size,single_level_column_mux.unique_id)
single_level_column_mux.unique_id += 1
design.design.__init__(self, name)
debug.info(2, "create single column mux cell: {0}".format(name))
@ -52,7 +55,7 @@ class single_level_column_mux(design.design):
self.bitcell = self.mod_bitcell()
# Adds nmos_lower,nmos_upper to the module
self.ptx_width = self.tx_size * drc("minwidth_tx")
self.ptx_width = self.tx_size*drc("minwidth_tx")
self.nmos = ptx(width=self.ptx_width)
self.add_mod(self.nmos)