mirror of https://github.com/VLSIDA/OpenRAM.git
Change default col mux size to 2. Add some comments.
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@ -61,8 +61,7 @@ class single_level_column_mux_array(design.design):
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def add_modules(self):
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# FIXME: Why is this 8x?
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self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
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self.mux = single_level_column_mux(bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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@ -9,13 +9,16 @@ from globals import OPTS
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class single_level_column_mux(design.design):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single columnmux cell.
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Creates a single columnmux cell with the given integer size relative
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to minimum size. Default is 2x.
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"""
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# This is needed for different bitline spacings
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unique_id = 1
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def __init__(self, tx_size, bitcell_bl="bl", bitcell_br="br"):
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name="single_level_column_mux_{}_no{}".format(tx_size,single_level_column_mux.unique_id)
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def __init__(self, tx_size=2, bitcell_bl="bl", bitcell_br="br"):
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self.tx_size = int(tx_size)
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name="single_level_column_mux_{}_{}".format(self.tx_size,single_level_column_mux.unique_id)
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single_level_column_mux.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "create single column mux cell: {0}".format(name))
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@ -52,7 +55,7 @@ class single_level_column_mux(design.design):
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self.bitcell = self.mod_bitcell()
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# Adds nmos_lower,nmos_upper to the module
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self.ptx_width = self.tx_size * drc("minwidth_tx")
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self.ptx_width = self.tx_size*drc("minwidth_tx")
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self.nmos = ptx(width=self.ptx_width)
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self.add_mod(self.nmos)
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