Merge branch 'dev' into supply_routing

.gitlab-ci.yml

@@ -1,6 +1,6 @@
 freepdk45:
   script: "/home/gitlab-runner/regress_freepdk45.sh"
 
-scn3me_subm:
-  script: "/home/gitlab-runner/regress_scn3me_subm.sh"
+scn4m_subm:
+  script: "/home/gitlab-runner/regress_scn4m_subm.sh"
 

compiler/base/hierarchy_layout.py

@@ -602,6 +602,7 @@ class layout(lef.lef):
         """ 
         Connect a mapping of pin -> name for a bus. This could be
         replaced with a channel router in the future. 
+        NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net).
         """
         (horizontal_layer, via_layer, vertical_layer)=layer_stack
         if horizontal:
@@ -711,16 +712,18 @@ class layout(lef.lef):
                 self.add_wire(layer_stack, [pin.center(), mid, trunk_mid])
         
     
-    def create_channel_route(self, route_map, top_pins, bottom_pins, offset, 
+    def create_channel_route(self, netlist, pins, offset, 
                              layer_stack=("metal1", "via1", "metal2"), pitch=None,
                              vertical=False):
         """
-        This is a simple channel route for one-to-one connections that
-        will jog the top route whenever there is a conflict. It does NOT
-        try to minimize the number of tracks -- instead, it picks an order to avoid the vertical
-        conflicts between pins.
-        """
+        The net list is a list of the nets. Each net is a list of pin
+        names to be connected.  Pins is a dictionary of the pin names
+        to the pin structures.  Offset is the lower-left of where the
+        routing channel will start.  This does NOT try to minimize the
+        number of tracks -- instead, it picks an order to avoid the
+        vertical conflicts between pins.
 
+        """
         def remove_net_from_graph(pin, g):
             # Remove the pin from the keys
             g.pop(pin,None)
@@ -732,11 +735,32 @@ class layout(lef.lef):
                     g[other_pin]=conflicts
             return g
 
+        def vcg_pins_overlap(pins1, pins2, vertical):
+            # Check all the pin pairs on two nets and return a pin
+            # overlap if any pin overlaps vertically
+            for pin1 in pins1:
+                for pin2 in pins2:
+                    if vcg_pin_overlap(pin1, pin2, vertical):
+                        return True
+
+            return False
+                            
+        def vcg_pin_overlap(pin1, pin2, vertical):
+            # Check for vertical overlap of the two pins
+
+            # Pin 1 must be in the "TOP" set
+            x_overlap = pin1.by() > pin2.by() and abs(pin1.center().x-pin2.center().x)<pitch
+
+            # Pin 1 must be in the "LET" set
+            y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y-pin2.center().y)<pitch
+            
+            return (not vertical and x_overlap) or (vertical and y_overlap)
+
+
+
         if not pitch:
             pitch = self.m2_pitch
 
-        # merge the two dictionaries to easily access all pins
-        all_pins = {**top_pins, **bottom_pins}
 
         # FIXME: Must extend this to a horizontal conflict graph too if we want to minimize the
         # number of tracks!
@@ -744,81 +768,90 @@ class layout(lef.lef):
         
         # Initialize the vertical conflict graph (vcg) and make a list of all pins
         vcg = {}
-        
+
+        # Create names for the nets for the graphs
+        nets = {}
+        index = 0
+        #print(netlist)
+        for pin_list in netlist:
+                net_name = "n{}".format(index)
+                index += 1
+                nets[net_name] = []
+                for pin_name in pin_list:
+                    pin = pins[pin_name]
+                    nets[net_name].append(pin)
+
         # Find the vertical pin conflicts
         # FIXME: O(n^2) but who cares for now
-        for top_name,top_pin in top_pins.items():
-            vcg[top_name]=[]    
-            for bot_name,bot_pin in bottom_pins.items():
-                # Remember, vertical is the boolean of the routes in the channel
-                # so check the intervals of the pins in the other dimension
-                x_overlap = abs(top_pin.center().x-bot_pin.center().x)<pitch
-                y_overlap = abs(top_pin.center().y-bot_pin.center().y)<pitch
-                             
-                if (vertical and y_overlap) or (not vertical and x_overlap):
+        for net_name1 in nets:
+            vcg[net_name1]=[]
+            for net_name2 in nets:
+                # Skip yourself
+                if net_name1 == net_name2:
+                    continue
+                if vcg_pins_overlap(nets[net_name1], nets[net_name2], vertical):
                     try:
-                        vcg[bot_name].append(top_name)
+                        vcg[net_name2].append(net_name1)
                     except:
-                        vcg[bot_name] = [top_name]
+                        vcg[net_name2] = [net_name1]
                     
         #FIXME: What if we have a cycle? 
 
-        # This is the starting offset of the first trunk
-        if vertical:
-            half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[2])]        
-            offset = offset + vector(half_minwidth,0)
-        else:
-            half_minwidth = 0.5*drc["minwidth_{}".format(layer_stack[0])]        
-            offset = offset + vector(0,half_minwidth)
+        # The starting offset is the first trunk at the top or left
+        # so we must offset from the lower left of the channel placement
+        # in the case of vertical tracks
+        if not vertical:
+            # This will start from top down
+            offset = offset + vector(0,len(nets)*pitch)
 
         # list of routes to do
         while vcg:
-            #print(vcg)
+            #from pprint import pformat
+            #print("VCG:\n",pformat(vcg))
             # get a route from conflict graph with empty fanout set
-            route_pin=None
-            for route_pin,conflicts in vcg.items():
+            net_name=None
+            for net_name,conflicts in vcg.items():
                 if len(conflicts)==0:
-                    vcg=remove_net_from_graph(route_pin,vcg)
+                    vcg=remove_net_from_graph(net_name,vcg)
                     break
+            else:
+                # FIXME: We don't support cyclic VCGs right now.
+                debug.error("Cyclic VCG in channel router.",-1)
 
-            # Get the connected pins from the routing map
-            for pin_connections in route_map:
-                if route_pin in pin_connections:
-                    break
-            #print("Routing:",route_pin,pin_connections)
-            
-            # Remove the other pins from the conflict graph too
-            for other_pin in pin_connections:
-                vcg=remove_net_from_graph(other_pin, vcg)
                 
-            # Create a list of the pins rather than a list of the names
-            pin_list = [all_pins[pin_name] for pin_name in pin_connections]
 
-            # Add the trunk route and move up to next track
+            # These are the pins we'll have to connect
+            pin_list = nets[net_name]
+            #print("Routing:",net_name,[x.name for x in pin_list])
+
+            # Remove the net from other constriants in the VCG
+            vcg=remove_net_from_graph(net_name, vcg)
+            
+            # Add the trunk routes from the bottom up or right to left
             if vertical:
                 self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
-                offset += vector(pitch,0)
+                offset -= vector(pitch,0)
             else:
                 self.add_horizontal_trunk_route(pin_list, offset, layer_stack, pitch)
-                offset += vector(0,pitch)
+                offset -= vector(0,pitch)
 
 
-    def create_vertical_channel_route(self, route_map, left_inst, right_inst, offset, 
+    def create_vertical_channel_route(self, netlist, pins, offset, 
                                       layer_stack=("metal1", "via1", "metal2"),
                                       pitch=None):
         """
         Wrapper to create a vertical channel route
         """
-        self.create_channel_route(route_map, left_inst, right_inst, offset,
-                                  layer_stack, pitch, vertical=True)
+        self.create_channel_route(netlist, pins, offset, layer_stack,
+                                  pitch, vertical=True)
 
-    def create_horizontal_channel_route(self, route_map, top_pins, bottom_pins, offset, 
-                                      layer_stack=("metal1", "via1", "metal2"),
-                                      pitch=None):
+    def create_horizontal_channel_route(self, netlist, pins, offset, 
+                                        layer_stack=("metal1", "via1", "metal2"),
+                                        pitch=None):
         """
         Wrapper to create a horizontal channel route
         """
-        self.create_channel_route(route_map, top_pins, bottom_pins, offset,
+        self.create_channel_route(netlist, pins, offset,
                                   layer_stack, pitch, vertical=False)
         
     def add_enclosure(self, insts, layer="nwell"):

compiler/characterizer/lib.py

@@ -12,18 +12,43 @@ class lib:
     """ lib file generation."""
     
     def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay):
+        #Temporary Workaround to here to set num of ports. Crashes if set in config file.
+        #OPTS.num_rw_ports = 2
+        #OPTS.num_r_ports = 1
+        #OPTS.num_w_ports = 1
+    
         self.out_dir = out_dir
         self.sram = sram
         self.sp_file = sp_file        
         self.use_model = use_model
-
+        self.gen_port_names() #copy and paste from delay.py, names are not final will likely be changed later.
+        
         self.prepare_tables()
         
         self.create_corners()
         
         self.characterize_corners()
         
-
+    def gen_port_names(self):
+        """Generates the port names to be written to the lib file"""
+        #This is basically a copy and paste of whats in delay.py as well. Something more efficient should be done here.
+        self.write_ports = []
+        self.read_ports = []
+        self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
+        
+        #save a member variable to avoid accessing global. readwrite ports have different control signals.
+        self.readwrite_port_num = OPTS.num_rw_ports
+        
+        #Generate the port names. readwrite ports are required to be added first for this to work.
+        for readwrite_port_num in range(OPTS.num_rw_ports):
+            self.read_ports.append(readwrite_port_num)
+            self.write_ports.append(readwrite_port_num)
+        #This placement is intentional. It makes indexing input data easier. See self.data_values
+        for read_port_num in range(OPTS.num_rw_ports, OPTS.num_r_ports):
+            self.read_ports.append(read_port_num)
+        for write_port_num in range(OPTS.num_rw_ports+OPTS.num_r_ports, OPTS.num_w_ports):
+            self.write_ports.append(write_port_num)
+        
     def prepare_tables(self):
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
@@ -85,13 +110,14 @@ class lib:
 
         self.write_header()
         
-        self.write_data_bus()
-        
-        self.write_addr_bus()
-        
-        self.write_control_pins()
-        
-        self.write_clk()
+        #Loop over all readwrite ports. This is debugging. Will change later.
+        for port in range(self.total_port_num):
+            #set the read and write port as inputs.
+            self.write_data_bus(port)
+            self.write_addr_bus(port)
+            self.write_control_pins(port) #need to split this into sram and port control signals
+            
+        self.write_clk_timing_power()
 
         self.write_footer()
 
@@ -127,9 +153,14 @@ class lib:
         self.lib.write("    dont_touch : true;\n")
         self.lib.write("    area : {};\n\n".format(self.sram.width * self.sram.height))
 
+        #Build string of all control signals. This is subject to change once control signals finalized.
+        control_str = 'CSb0' #assume at least 1 port
+        for i in range(1, self.total_port_num):
+            control_str += ' & CSb{0}'.format(i)
+            
         # Leakage is included in dynamic when macro is enabled
         self.lib.write("    leakage_power () {\n")
-        self.lib.write("      when : \"CSb\";\n")
+        self.lib.write("      when : \"{0}\";\n".format(control_str))
         self.lib.write("      value : {};\n".format(self.char_results["leakage_power"]))
         self.lib.write("    }\n")
         self.lib.write("    cell_leakage_power : {};\n".format(0))
@@ -295,65 +326,72 @@ class lib:
         self.lib.write("            }\n")
         self.lib.write("        }\n")
 
-
-
-    def write_data_bus(self):
+    def write_data_bus_output(self, read_port):
         """ Adds data bus timing results."""
 
-        self.lib.write("    bus(DIN){\n")
+        self.lib.write("    bus(DOUT{0}){{\n".format(read_port))
         self.lib.write("        bus_type  : DATA; \n")
-        self.lib.write("        direction  : in; \n")
-        # This is conservative, but limit to range that we characterized.
-        self.lib.write("        max_capacitance : {0};  \n".format(max(self.loads)))
-        self.lib.write("        min_capacitance : {0};  \n".format(min(self.loads)))        
-        self.lib.write("        memory_write(){ \n")
-        self.lib.write("            address : ADDR; \n")
-        self.lib.write("            clocked_on  : clk; \n")
-        self.lib.write("        }\n")
-
-        self.lib.write("    bus(DOUT){\n")
-        self.lib.write("        bus_type  : DATA; \n")
-        self.lib.write("        direction  : out; \n")
+        self.lib.write("        direction  : output; \n")
         # This is conservative, but limit to range that we characterized.
         self.lib.write("        max_capacitance : {0};  \n".format(max(self.loads)))
         self.lib.write("        min_capacitance : {0};  \n".format(min(self.loads)))        
         self.lib.write("        memory_read(){ \n")
-        self.lib.write("            address : ADDR; \n")
+        self.lib.write("            address : ADDR{0}; \n".format(read_port))
         self.lib.write("        }\n")
         
 
-        self.lib.write("        pin(DOUT[{0}:0]){{\n".format(self.sram.word_size - 1))
+        self.lib.write("        pin(DOUT{1}[{0}:0]){{\n".format(self.sram.word_size - 1, read_port))
         self.write_FF_setuphold()
         self.lib.write("        timing(){ \n")
         self.lib.write("            timing_sense : non_unate; \n")
         self.lib.write("            related_pin : \"clk\"; \n")
         self.lib.write("            timing_type : rising_edge; \n")
         self.lib.write("            cell_rise(CELL_TABLE) {\n")
-        self.write_values(self.char_results["delay_lh"],len(self.loads),"            ")
+        self.write_values(self.char_results["delay_lh{0}".format(read_port)],len(self.loads),"            ")
         self.lib.write("            }\n") # rise delay
         self.lib.write("            cell_fall(CELL_TABLE) {\n")
-        self.write_values(self.char_results["delay_hl"],len(self.loads),"            ")
+        self.write_values(self.char_results["delay_hl{0}".format(read_port)],len(self.loads),"            ")
         self.lib.write("            }\n") # fall delay
         self.lib.write("            rise_transition(CELL_TABLE) {\n")
-        self.write_values(self.char_results["slew_lh"],len(self.loads),"            ")
+        self.write_values(self.char_results["slew_lh{0}".format(read_port)],len(self.loads),"            ")
         self.lib.write("            }\n") # rise trans
         self.lib.write("            fall_transition(CELL_TABLE) {\n")
-        self.write_values(self.char_results["slew_hl"],len(self.loads),"            ")
+        self.write_values(self.char_results["slew_hl{0}".format(read_port)],len(self.loads),"            ")
         self.lib.write("            }\n") # fall trans
         self.lib.write("        }\n") # timing
         self.lib.write("        }\n") # pin        
         self.lib.write("    }\n\n") # bus
 
+    def write_data_bus_input(self, write_port):
+        """ Adds data bus timing results."""
 
-    def write_addr_bus(self):
+        self.lib.write("    bus(DIN{0}){{\n".format(write_port))
+        self.lib.write("        bus_type  : DATA; \n")
+        self.lib.write("        direction  : input; \n")
+        # This is conservative, but limit to range that we characterized.
+        self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
+        self.lib.write("        memory_write(){ \n")
+        self.lib.write("            address : ADDR{0}; \n".format(write_port))
+        self.lib.write("            clocked_on  : clk; \n")
+        self.lib.write("        }\n")
+        self.lib.write("    }\n")
+
+    def write_data_bus(self, port):
+        """ Adds data bus timing results."""
+        if port in self.write_ports:
+            self.write_data_bus_input(port)
+        if port in self.read_ports:
+            self.write_data_bus_output(port)
+
+    def write_addr_bus(self, port):
         """ Adds addr bus timing results."""
-
-        self.lib.write("    bus(ADDR){\n")
+        
+        self.lib.write("    bus(ADDR{0}){{\n".format(port))
         self.lib.write("        bus_type  : ADDR; \n")
         self.lib.write("        direction  : input; \n")
         self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
         self.lib.write("        max_transition       : {0};\n".format(self.slews[-1]))
-        self.lib.write("        pin(ADDR[{0}:0])".format(self.sram.addr_size - 1))
+        self.lib.write("        pin(ADDR{1}[{0}:0])".format(self.sram.addr_size - 1, port))
         self.lib.write("{\n")
         
         self.write_FF_setuphold()
@@ -361,10 +399,13 @@ class lib:
         self.lib.write("    }\n\n")
 
 
-    def write_control_pins(self):
+    def write_control_pins(self, port):
         """ Adds control pins timing results."""
-
-        ctrl_pin_names = ["CSb", "OEb", "WEb"]
+        #The control pins are still to be determined. This is a placeholder for what could be.
+        ctrl_pin_names = ["CSb{0}".format(port)]
+        if port in self.write_ports and port in self.read_ports:
+            ctrl_pin_names.append("WEb{0}".format(port))
+            
         for i in ctrl_pin_names:
             self.lib.write("    pin({0})".format(i))
             self.lib.write("{\n")
@@ -373,8 +414,7 @@ class lib:
             self.write_FF_setuphold()
             self.lib.write("    }\n\n")
 
-
-    def write_clk(self):
+    def write_clk_timing_power(self):
         """ Adds clk pin timing results."""
 
         self.lib.write("    pin(clk){\n")
@@ -383,41 +423,10 @@ class lib:
         # FIXME: This depends on the clock buffer size in the control logic
         self.lib.write("        capacitance : {0};  \n".format(tech.spice["dff_in_cap"]))
 
-        # Find the average power of 1 and 0 bits for writes and reads over all loads/slews
-        # Could make it a table, but this is fine for now.
-        avg_write_power = np.mean(self.char_results["write1_power"] + self.char_results["write0_power"])
-        avg_read_power = np.mean(self.char_results["read1_power"] + self.char_results["read0_power"])        
-
-        # Equally divide read/write power between first and second half of clock period
-        self.lib.write("        internal_power(){\n")
-        self.lib.write("            when : \"!CSb & clk & !WEb\"; \n")
-        self.lib.write("            rise_power(scalar){\n")
-        self.lib.write("                values(\"{0}\");\n".format(avg_write_power/2.0))
-        self.lib.write("            }\n")
-        self.lib.write("            fall_power(scalar){\n")
-        self.lib.write("                values(\"{0}\");\n".format(avg_write_power/2.0))
-        self.lib.write("            }\n")
-        self.lib.write("        }\n")
-
-        self.lib.write("        internal_power(){\n")
-        self.lib.write("            when : \"!CSb & !clk & WEb\"; \n")
-        self.lib.write("            rise_power(scalar){\n")
-        self.lib.write("                values(\"{0}\");\n".format(avg_read_power/2.0))
-        self.lib.write("            }\n")
-        self.lib.write("            fall_power(scalar){\n")
-        self.lib.write("                values(\"{0}\");\n".format(avg_read_power/2.0))
-        self.lib.write("            }\n")
-        self.lib.write("        }\n")
-        # Have 0 internal power when disabled, this will be represented as leakage power.
-        self.lib.write("        internal_power(){\n")
-        self.lib.write("            when : \"CSb\"; \n")
-        self.lib.write("            rise_power(scalar){\n")
-        self.lib.write("                values(\"0\");\n")
-        self.lib.write("            }\n")
-        self.lib.write("            fall_power(scalar){\n")
-        self.lib.write("                values(\"0\");\n")
-        self.lib.write("            }\n")
-        self.lib.write("        }\n")
+        #Add power values for the ports. lib generated with this is not syntactically correct. TODO once
+        #top level is done.
+        for port in range(self.total_port_num):
+            self.add_clk_control_power(port)
 
         min_pulse_width = round_time(self.char_results["min_period"])/2.0
         min_period = round_time(self.char_results["min_period"])
@@ -443,7 +452,51 @@ class lib:
         self.lib.write("         }\n")
         self.lib.write("    }\n")
         self.lib.write("    }\n")
+    
+    def add_clk_control_power(self, port):
+        """Writes powers under the clock pin group for a specified port"""
+        #Web added to read/write ports. Likely to change when control logic finished.
+        web_name = ""
+            
+        if port in self.write_ports:
+            if port in self.read_ports:
+                web_name = " & !WEb{0}".format(port)
+            avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
+            self.lib.write("        internal_power(){\n")
+            self.lib.write("            when : \"!CSb{0} & clk{1}\"; \n".format(port, web_name))
+            self.lib.write("            rise_power(scalar){\n")
+            self.lib.write("                values(\"{0}\");\n".format(avg_write_power/2.0))
+            self.lib.write("            }\n")
+            self.lib.write("            fall_power(scalar){\n")
+            self.lib.write("                values(\"{0}\");\n".format(avg_write_power/2.0))
+            self.lib.write("            }\n")
+            self.lib.write("        }\n")
 
+        if port in self.read_ports:
+            if port in self.write_ports:
+                web_name = " & WEb{0}".format(port)
+            avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])
+            self.lib.write("        internal_power(){\n")
+            self.lib.write("            when : \"!CSb{0} & !clk{1}\"; \n".format(port, web_name))
+            self.lib.write("            rise_power(scalar){\n")
+            self.lib.write("                values(\"{0}\");\n".format(avg_read_power/2.0))
+            self.lib.write("            }\n")
+            self.lib.write("            fall_power(scalar){\n")
+            self.lib.write("                values(\"{0}\");\n".format(avg_read_power/2.0))
+            self.lib.write("            }\n")
+            self.lib.write("        }\n")
+            
+        # Have 0 internal power when disabled, this will be represented as leakage power.
+        self.lib.write("        internal_power(){\n")
+        self.lib.write("            when : \"CSb{0}\"; \n".format(port))
+        self.lib.write("            rise_power(scalar){\n")
+        self.lib.write("                values(\"0\");\n")
+        self.lib.write("            }\n")
+        self.lib.write("            fall_power(scalar){\n")
+        self.lib.write("                values(\"0\");\n")
+        self.lib.write("            }\n")
+        self.lib.write("        }\n")
+        
     def compute_delay(self):
         """ Do the analysis if we haven't characterized the SRAM yet """
         if not hasattr(self,"d"):

compiler/characterizer/setup_hold.py

@@ -3,7 +3,7 @@ import tech
 from .stimuli import *
 import debug
 from .charutils import *
-import ms_flop
+import dff
 from globals import OPTS
 
 
@@ -15,9 +15,9 @@ class setup_hold():
 
     def __init__(self, corner):
         # This must match the spice model order
-        self.pins = ["data", "dout", "dout_bar", "clk", "vdd", "gnd"]
-        self.model_name = "ms_flop"
-        self.model_location = OPTS.openram_tech + "sp_lib/ms_flop.sp"
+        self.pins = ["data", "dout", "clk", "vdd", "gnd"]
+        self.model_name = "dff"
+        self.model_location = OPTS.openram_tech + "sp_lib/dff.sp"
         self.period = tech.spice["feasible_period"]
 
         debug.info(2,"Feasible period from technology file: {0} ".format(self.period))
@@ -276,17 +276,36 @@ class setup_hold():
         HL_setup = []
         LH_hold = []
         HL_hold = []
+        
+        #For debugging, skips characterization and returns dummy values.
+        # i = 1.0
+        # for self.related_input_slew in related_slews:
+            # for self.constrained_input_slew in constrained_slews:
+                # LH_setup.append(i)
+                # HL_setup.append(i+1.0)
+                # LH_hold.append(i+2.0)
+                # HL_hold.append(i+3.0)
+                # i+=4.0
+                
+        # times = {"setup_times_LH": LH_setup,
+                 # "setup_times_HL": HL_setup,
+                 # "hold_times_LH": LH_hold,
+                 # "hold_times_HL": HL_hold
+                 # }
+        # return times
+        
+        
         for self.related_input_slew in related_slews:
             for self.constrained_input_slew in constrained_slews:
                 debug.info(1, "Clock slew: {0} Data slew: {1}".format(self.related_input_slew,self.constrained_input_slew))
                 LH_setup_time = self.setup_LH_time()
-                debug.info(1, "  Setup Time for low_to_high transistion: {0}".format(LH_setup_time))
+                debug.info(1, "  Setup Time for low_to_high transition: {0}".format(LH_setup_time))
                 HL_setup_time = self.setup_HL_time()
-                debug.info(1, "  Setup Time for high_to_low transistion: {0}".format(HL_setup_time))
+                debug.info(1, "  Setup Time for high_to_low transition: {0}".format(HL_setup_time))
                 LH_hold_time = self.hold_LH_time()
-                debug.info(1, "  Hold Time for low_to_high transistion: {0}".format(LH_hold_time))
+                debug.info(1, "  Hold Time for low_to_high transition: {0}".format(LH_hold_time))
                 HL_hold_time = self.hold_HL_time()
-                debug.info(1, "  Hold Time for high_to_low transistion: {0}".format(HL_hold_time))
+                debug.info(1, "  Hold Time for high_to_low transition: {0}".format(HL_hold_time))
                 LH_setup.append(LH_setup_time)
                 HL_setup.append(HL_setup_time)
                 LH_hold.append(LH_hold_time)

compiler/characterizer/stimuli.py

@@ -30,18 +30,33 @@ class stimuli():
         self.device_models = tech.spice["fet_models"][self.process]
 
     
-    def inst_sram(self, abits, dbits, sram_name):
+    def inst_sram(self, abits, dbits, port_info, sram_name):
         """ Function to instatiate an SRAM subckt. """
         self.sf.write("Xsram ")
-        for i in range(dbits):
-            self.sf.write("DIN[{0}] ".format(i))
-        for i in range(abits):
-            self.sf.write("A[{0}] ".format(i))
-        for i in tech.spice["control_signals"]:
-            self.sf.write("{0} ".format(i))
+        
+        #Un-tuple the port names. This was done to avoid passing them all as arguments. Could be improved still.
+        #This should be generated from the pin list of the sram... change when multiport pins done.
+        (total_port_num,readwrite_num,read_ports,write_ports) = port_info
+
+        for write_input in write_ports:
+            for i in range(dbits):
+                self.sf.write("DIN{0}[{1}] ".format(write_input, i))
+        
+        for port in range(total_port_num):
+            for i in range(abits):
+                self.sf.write("A{0}[{1}] ".format(port,i))    
+
+        #These control signals assume 6t sram i.e. a single readwrite port. If multiple readwrite ports are used then add more
+        #control signals. Not sure if this is correct, consider a temporary change until control signals for multiport are finalized.
+        for port in range(total_port_num):
+            self.sf.write("CSB{0} ".format(port))
+        for readwrite_port in range(readwrite_num):
+            self.sf.write("WEB{0} ".format(readwrite_port))
+            
         self.sf.write("{0} ".format(tech.spice["clk"]))
-        for i in range(dbits):
-            self.sf.write("DOUT[{0}] ".format(i))
+        for read_output in read_ports:
+            for i in range(dbits):
+                self.sf.write("DOUT{0}[{1}] ".format(read_output, i))
         self.sf.write("{0} {1} ".format(self.vdd_name, self.gnd_name))
         self.sf.write("{0}\n".format(sram_name))
 

compiler/example_config_freepdk45.py

@@ -10,3 +10,10 @@ temperatures = [25]
 output_path = "temp"
 output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
 
+#Below are some additions to test additional ports on sram
+#bitcell = "pbitcell"
+
+# These are the configuration parameters
+#rw_ports = 2
+#r_ports = 2
+#w_ports = 2

compiler/example_config_scn3me_subm.py

@@ -9,4 +9,3 @@ temperatures = [ 25 ]
 
 output_path = "temp"
 output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
-

compiler/globals.py

@@ -59,7 +59,7 @@ def parse_args():
         OPTS.tech_name = "scmos"
     # Alias SCMOS to AMI 0.5um
     if OPTS.tech_name == "scmos":
-        OPTS.tech_name = "scn3me_subm"
+        OPTS.tech_name = "scn4m_subm"
 
     return (options, args)
 

compiler/modules/bank.py

@@ -67,10 +67,21 @@ class bank(design.design):
         self.DRC_LVS()
         
     def add_pins(self):
+        self.read_index = []
+        port_number = 0
+        for port in range(OPTS.num_rw_ports):
+            self.read_index.append("{}".format(port_number))
+            port_number += 1
+        for port in range(OPTS.num_w_ports):
+            port_number += 1
+        for port in range(OPTS.num_r_ports):
+            self.read_index.append("{}".format(port_number))
+            port_number += 1
+        
         """ Adding pins for Bank module"""
         for port in range(self.total_read):
             for bit in range(self.word_size):
-                self.add_pin("dout{0}[{1}]".format(port,bit),"OUT")
+                self.add_pin("dout{0}[{1}]".format(self.read_index[port],bit),"OUT")
         for port in range(self.total_write):
             for bit in range(self.word_size):
                 self.add_pin("din{0}[{1}]".format(port,bit),"IN")
@@ -84,7 +95,7 @@ class bank(design.design):
             for port in range(self.total_ports):
                 self.add_pin("bank_sel{}".format(port),"INPUT")
         for port in range(self.total_read):
-            self.add_pin("s_en{0}".format(port), "INPUT")
+            self.add_pin("s_en{0}".format(self.read_index[port]), "INPUT")
         for port in range(self.total_write):
             self.add_pin("w_en{0}".format(port), "INPUT")
         for pin in ["clk_buf_bar","clk_buf"]:
@@ -195,7 +206,7 @@ class bank(design.design):
     def add_modules(self):
         """ Create all the modules using the class loader """
         
-        mod_list = ["bitcell", "decoder", "ms_flop_array", "wordline_driver",
+        mod_list = ["bitcell", "decoder", "wordline_driver",
                     "bitcell_array",   "sense_amp_array",    "precharge_array",
                     "column_mux_array", "write_driver_array", 
                     "dff", "bank_select"]
@@ -232,9 +243,13 @@ class bank(design.design):
             self.add_mod(self.precharge_array[port])
 
         if self.col_addr_size > 0:
-            self.column_mux_array = self.mod_column_mux_array(columns=self.num_cols, 
-                                                              word_size=self.word_size)
-            self.add_mod(self.column_mux_array)
+            self.column_mux_array = []
+            for port in range(self.total_ports):
+                self.column_mux_array.append(self.mod_column_mux_array(columns=self.num_cols, 
+                                                                       word_size=self.word_size,
+                                                                       bitcell_bl=self.read_bl_list[port],
+                                                                       bitcell_br=self.read_br_list[port]))
+                self.add_mod(self.column_mux_array[port])
 
 
         self.sense_amp_array = self.mod_sense_amp_array(word_size=self.word_size, 
@@ -314,7 +329,7 @@ class bank(design.design):
         self.col_mux_array_inst = []
         for port in range(self.total_ports):
             self.col_mux_array_inst.append(self.add_inst(name="column_mux_array{}".format(port),
-                                                         mod=self.column_mux_array))
+                                                         mod=self.column_mux_array[port]))
 
             temp = []
             for col in range(self.num_cols):
@@ -331,7 +346,7 @@ class bank(design.design):
     def place_column_mux_array(self):
         """ Placing Column Mux when words_per_row > 1 . """
         if self.col_addr_size > 0:
-            self.column_mux_height = self.column_mux_array.height + self.m2_gap
+            self.column_mux_height = self.column_mux_array[0].height + self.m2_gap
         else:
             self.column_mux_height = 0
             return
@@ -350,7 +365,7 @@ class bank(design.design):
 
             temp = []
             for bit in range(self.word_size):
-                temp.append("dout{0}[{1}]".format(port,bit))
+                temp.append("dout{0}[{1}]".format(self.read_index[port],bit))
                 if self.words_per_row == 1:
                     temp.append(self.read_bl_list[port]+"[{0}]".format(bit))
                     temp.append(self.read_br_list[port]+"[{0}]".format(bit))
@@ -547,29 +562,35 @@ class bank(design.design):
 
         # These are the instances that every bank has
         top_instances = [self.bitcell_array_inst]
-
+        for port in range(self.total_read):
+            #top_instances.append(self.precharge_array_inst[port])
+            top_instances.append(self.sense_amp_array_inst[port])
+        for port in range(self.total_write):
+            top_instances.append(self.write_driver_array_inst[port])
         for port in range(self.total_ports):
-            top_instances.extend([self.precharge_array_inst[port],
-                                  self.sense_amp_array_inst[port],
-                                  self.write_driver_array_inst[port],
-                                  self.row_decoder_inst[port],
+            top_instances.extend([self.row_decoder_inst[port],
                                   self.wordline_driver_inst[port]])
             # Add these if we use the part...
             if self.col_addr_size > 0:
                 top_instances.append(self.col_decoder_inst[port])
-                top_instances.append(self.col_mux_array_inst[port])
+                #top_instances.append(self.col_mux_array_inst[port])
             
             if self.num_banks > 1:
                 top_instances.append(self.bank_select_inst[port])
-
+        
+        if self.col_addr_size > 0:
+            for port in range(self.total_ports):
+                self.copy_layout_pin(self.col_mux_array_inst[port], "gnd")
+        for port in range(self.total_read):
+            self.copy_layout_pin(self.precharge_array_inst[port], "vdd")
         
         for inst in top_instances:
             # Column mux has no vdd
-            if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst[0]):
-                self.copy_layout_pin(inst, "vdd")
+            #if self.col_addr_size==0 or (self.col_addr_size>0 and inst != self.col_mux_array_inst[0]):
+            self.copy_layout_pin(inst, "vdd")
             # Precharge has no gnd
-            if inst != self.precharge_array_inst[0]:
-                self.copy_layout_pin(inst, "gnd")
+            #if inst != self.precharge_array_inst[port]:
+            self.copy_layout_pin(inst, "gnd")
         
     def route_bank_select(self):
         """ Route the bank select logic. """

compiler/modules/bitcell.py

@@ -50,16 +50,6 @@ class bitcell(design.design):
         row_pins = ["wl"]    
         return row_pins
     
-    def list_read_wl_names(self):
-        """ Creates a list of wordline pin names associated with read ports """
-        row_pins = ["wl"]    
-        return row_pins
-        
-    def list_write_wl_names(self):
-        """ Creates a list of wordline pin names associated with write ports """
-        row_pins = ["wl"]    
-        return row_pins
-    
     def list_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
         column_pins = ["bl", "br"]

compiler/modules/control_logic.py

@@ -96,7 +96,7 @@ class control_logic(design.design):
         """ Setup bus names, determine the size of the busses etc """
 
         # List of input control signals
-        self.input_list =["csb","web"]
+        self.input_list =["csb","web0"]
         self.dff_output_list =["cs_bar", "cs", "we_bar", "we"]        
         # list of output control signals (for making a vertical bus)
         self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"]
@@ -267,7 +267,7 @@ class control_logic(design.design):
         
         # Connect the clock rail to the other clock rail
         in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
-        mid_pos = in_pos + vector(0,self.m2_pitch)
+        mid_pos = in_pos + vector(0,2*self.m2_pitch)
         rail_pos = vector(self.rail_offsets["clk_buf"].x, mid_pos.y)
         self.add_wire(("metal1","via1","metal2"),[in_pos, mid_pos, rail_pos])
         self.add_via_center(layers=("metal1","via1","metal2"),
@@ -275,7 +275,7 @@ class control_logic(design.design):
                             rotate=90)
 
         self.copy_layout_pin(self.ctrl_dff_inst, "din[0]", "csb")
-        self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web")
+        self.copy_layout_pin(self.ctrl_dff_inst, "din[1]", "web0")
         
         
     def create_dffs(self):

compiler/modules/dff.py

@@ -21,6 +21,25 @@ class dff(design.design):
         self.height = dff.height
         self.pin_map = dff.pin_map
     
+    def analytical_power(self, proc, vdd, temp, load):
+        """Returns dynamic and leakage power. Results in nW"""
+        from tech import spice
+        c_eff = self.calculate_effective_capacitance(load)
+        f = spice["default_event_rate"]
+        power_dyn = c_eff*vdd*vdd*f
+        power_leak = spice["msflop_leakage"]
+        
+        total_power = self.return_power(power_dyn, power_leak)
+        return total_power
+        
+    def calculate_effective_capacitance(self, load):
+        """Computes effective capacitance. Results in fF"""
+        from tech import spice, parameter
+        c_load = load
+        c_para = spice["flop_para_cap"]#ff
+        transition_prob = spice["flop_transition_prob"]
+        return transition_prob*(c_load + c_para) 
+
     def analytical_delay(self, slew, load = 0.0):
         # dont know how to calculate this now, use constant in tech file
         from tech import spice

compiler/modules/hierarchical_predecode.py

@@ -56,8 +56,8 @@ class hierarchical_predecode(design.design):
         # x offset for input inverters
         self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch 
 
-        # x offset to NAND decoder includes the left rails, mid rails and inverters, plus an extra m2 pitch
-        self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 1) * self.m2_pitch
+        # x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches
+        self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch
 
         # x offset to output inverters
         self.x_off_inv_2 = self.x_off_nand + self.nand.width
@@ -78,7 +78,7 @@ class hierarchical_predecode(design.design):
         invert_names = ["Abar[{}]".format(x) for x in range(self.number_of_inputs)]
         non_invert_names = ["A[{}]".format(x) for x in range(self.number_of_inputs)]
         decode_names = invert_names + non_invert_names
-        offset = vector(self.x_off_inv_1 + self.inv.width + self.m2_pitch, 2*self.m1_width)
+        offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width)
         self.decode_rails = self.create_vertical_bus(layer="metal2",
                                                      pitch=self.m2_pitch,
                                                      offset=offset,

compiler/modules/ms_flop.py

@@ -1,50 +0,0 @@
-import globals
-import design
-from math import log
-import design
-from tech import GDS,layer
-import utils
-
-class ms_flop(design.design):
-    """
-    Memory address flip-flop
-    """
-
-    pin_names = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"]
-    (width,height) = utils.get_libcell_size("ms_flop", GDS["unit"], layer["boundary"])
-    pin_map = utils.get_libcell_pins(pin_names, "ms_flop", GDS["unit"], layer["boundary"])
-    
-    def __init__(self, name="ms_flop"):
-        design.design.__init__(self, name)
-
-        self.width = ms_flop.width
-        self.height = ms_flop.height
-        self.pin_map = ms_flop.pin_map
-    
-    def analytical_delay(self, slew, load = 0.0):
-        # dont know how to calculate this now, use constant in tech file
-        from tech import spice
-        result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
-        return result
-        
-    def analytical_power(self, proc, vdd, temp, load):
-        """Returns dynamic and leakage power. Results in nW"""
-        from tech import spice
-        c_eff = self.calculate_effective_capacitance(load)
-        f = spice["default_event_rate"]
-        power_dyn = c_eff*vdd*vdd*f
-        power_leak = spice["msflop_leakage"]
-        
-        total_power = self.return_power(power_dyn, power_leak)
-        return total_power
-        
-    def calculate_effective_capacitance(self, load):
-        """Computes effective capacitance. Results in fF"""
-        from tech import spice, parameter
-        c_load = load
-        c_para = spice["flop_para_cap"]#ff
-        transistion_prob = spice["flop_transisition_prob"]
-        return transistion_prob*(c_load + c_para) 
-
-        
-        

compiler/modules/ms_flop_array.py

@@ -1,136 +0,0 @@
-import debug
-import design
-from tech import drc
-from math import log
-from vector import vector
-from globals import OPTS
-
-class ms_flop_array(design.design):
-    """
-    An Array of D-Flipflops used for to store Data_in & Data_out of
-    Write_driver & Sense_amp, address inputs of column_mux &
-    hierdecoder
-    """
-
-    def __init__(self, columns, word_size, name=""):
-        self.columns = columns
-        self.word_size = word_size
-        if name=="":
-            name = "flop_array_c{0}_w{1}".format(columns,word_size)
-        design.design.__init__(self, name)
-        debug.info(1, "Creating {}".format(self.name))
-
-        self.words_per_row = int(self.columns / self.word_size)
-
-        self.create_netlist()
-        if not OPTS.netlist_only:
-            self.create_layout()
-
-    def create_netlist(self):
-        self.add_modules()
-        self.add_pins()
-        self.create_ms_flop_array()
-
-    def create_layout(self):
-        self.width = self.columns * self.ms.width
-        self.height = self.ms.height
-
-        self.place_ms_flop_array()
-        self.add_layout_pins()
-        self.DRC_LVS()
-
-    def add_modules(self):
-        from importlib import reload
-        c = reload(__import__(OPTS.ms_flop))
-        self.mod_ms_flop = getattr(c, OPTS.ms_flop)
-        self.ms = self.mod_ms_flop("ms_flop")
-        self.add_mod(self.ms)
-        
-    def add_pins(self):
-        for i in range(self.word_size):
-            self.add_pin("din[{0}]".format(i))
-        for i in range(self.word_size):
-            self.add_pin("dout[{0}]".format(i))
-            self.add_pin("dout_bar[{0}]".format(i))
-        self.add_pin("clk")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
-
-    def create_ms_flop_array(self):
-        self.ms_inst={}
-        for i in range(0,self.columns,self.words_per_row):
-            name = "Xdff{0}".format(i)
-            index = int(i/self.words_per_row)
-            self.ms_inst[index]=self.add_inst(name=name,
-                                              mod=self.ms)
-            self.connect_inst(["din[{0}]".format(index),
-                               "dout[{0}]".format(index),
-                               "dout_bar[{0}]".format(index),
-                               "clk",
-                               "vdd", "gnd"])
-
-    def place_ms_flop_array(self):
-        for i in range(0,self.columns,self.words_per_row):
-            index = int(i/self.words_per_row)
-            if (i % 2 == 0 or self.words_per_row>1):
-                base = vector(i*self.ms.width,0)
-                mirror = "R0"
-            else:
-                base = vector((i+1)*self.ms.width,0)
-                mirror = "MY"
-            self.ms_inst[index].place(offset=base, 
-                                      mirror=mirror)
-            
-    def add_layout_pins(self):
-        
-        for i in range(self.word_size):
-
-            # Route both supplies
-            for n in ["vdd", "gnd"]:
-                for supply_pin in self.ms_inst[i].get_pins(n):
-                    pin_pos = supply_pin.center()
-                    self.add_via_center(layers=("metal2", "via2", "metal3"),
-                                        offset=pin_pos)
-                    self.add_layout_pin_rect_center(text=n,
-                                                    layer="metal3",
-                                                    offset=pin_pos)
-                
-
-            din_pins = self.ms_inst[i].get_pins("din")
-            for din_pin in din_pins:
-                self.add_layout_pin(text="din[{}]".format(i),
-                                    layer=din_pin.layer,
-                                    offset=din_pin.ll(),
-                                    width=din_pin.width(),
-                                    height=din_pin.height())
-
-            dout_pin = self.ms_inst[i].get_pin("dout")
-            self.add_layout_pin(text="dout[{}]".format(i),
-                                layer="metal2",
-                                offset=dout_pin.ll(),
-                                width=dout_pin.width(),
-                                height=dout_pin.height())
-
-            doutbar_pin = self.ms_inst[i].get_pin("dout_bar")
-            self.add_layout_pin(text="dout_bar[{}]".format(i),
-                                layer="metal2",
-                                offset=doutbar_pin.ll(),
-                                width=doutbar_pin.width(),
-                                height=doutbar_pin.height())
-            
-            
-        # Continous clk rail along with label.
-        self.add_layout_pin(text="clk",
-                            layer="metal1",
-                            offset=self.ms_inst[0].get_pin("clk").ll().scale(0,1),
-                            width=self.width,
-                            height=drc["minwidth_metal1"])
-
-
-
-        
-            
-
-    def analytical_delay(self, slew, load=0.0):
-        return self.ms.analytical_delay(slew=slew, load=load)
-        

compiler/modules/multibank.py

@@ -23,7 +23,7 @@ class multibank(design.design):
 
     def __init__(self, word_size, num_words, words_per_row, num_banks=1, name=""):
 
-        mod_list = ["tri_gate", "bitcell", "decoder", "ms_flop_array", "wordline_driver",
+        mod_list = ["tri_gate", "bitcell", "decoder", "wordline_driver",
                     "bitcell_array",   "sense_amp_array",    "precharge_array",
                     "column_mux_array", "write_driver_array", "tri_gate_array",
                     "dff", "bank_select"]

compiler/modules/replica_bitline.py

@@ -128,7 +128,22 @@ class replica_bitline(design.design):
 
         self.rbl_inst=self.add_inst(name="load",
                                     mod=self.rbl)
-        self.connect_inst(["bl[0]", "br[0]"] + ["gnd"]*self.bitcell_loads + ["vdd", "gnd"])
+        
+        total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
+        temp = []
+        temp.append("bl[0]")
+        temp.append("br[0]")
+        for port in range(total_ports - 1):
+            temp.append("gnd")
+            temp.append("gnd")
+        for wl in range(self.bitcell_loads):
+            for port in range(total_ports):
+                temp.append("gnd")
+        temp.append("vdd")
+        temp.append("gnd")
+        self.connect_inst(temp)
+        
+        self.wl_list = self.rbl.cell.list_all_wl_names()
         
     def place_modules(self):
         """ Add all of the module instances in the logical netlist """
@@ -160,7 +175,7 @@ class replica_bitline(design.design):
         """ Connect the RBL word lines to gnd """
         # Connect the WL and gnd pins directly to the center and right gnd rails
         for row in range(self.bitcell_loads):
-            wl = "wl[{}]".format(row)
+            wl = self.wl_list[0]+"[{}]".format(row)
             pin = self.rbl_inst.get_pin(wl)
 
             # Route the connection to the right so that it doesn't interfere
@@ -371,7 +386,7 @@ class replica_bitline(design.design):
         
         # Connect the WL and gnd pins directly to the center and right gnd rails
         for row in range(self.bitcell_loads):
-            wl = "wl[{}]".format(row)
+            wl = self.wl_list[0]+"[{}]".format(row)
             pin = self.rbl_inst.get_pin(wl)
             if pin.layer != "metal1":
                 continue

compiler/modules/single_level_column_mux_array.py

@@ -14,12 +14,18 @@ class single_level_column_mux_array(design.design):
     Array of column mux to read the bitlines through the 6T.
     """
 
-    def __init__(self, columns, word_size):
-        design.design.__init__(self, "columnmux_array")
+    unique_id = 1
+    
+    def __init__(self, columns, word_size, bitcell_bl="bl", bitcell_br="br"):
+        name="single_level_column_mux_array_{}".format(single_level_column_mux_array.unique_id)
+        single_level_column_mux_array.unique_id += 1
+        design.design.__init__(self, name)
         debug.info(1, "Creating {0}".format(self.name))
         self.columns = columns
         self.word_size = word_size
         self.words_per_row = int(self.columns / self.word_size)
+        self.bitcell_bl = bitcell_bl
+        self.bitcell_br = bitcell_br
         
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -56,7 +62,7 @@ class single_level_column_mux_array(design.design):
 
     def add_modules(self):
         # FIXME: Why is this 8x?
-        self.mux = single_level_column_mux(tx_size=8)
+        self.mux = single_level_column_mux(tx_size=8, bitcell_bl=self.bitcell_bl, bitcell_br=self.bitcell_br)
         self.add_mod(self.mux)
 
 

compiler/modules/wordline_driver.py

@@ -52,10 +52,6 @@ class wordline_driver(design.design):
     def add_modules(self):
         # This is just used for measurements,
         # so don't add the module
-        from importlib import reload
-        c = reload(__import__(OPTS.bitcell))
-        self.mod_bitcell = getattr(c, OPTS.bitcell)
-        self.bitcell = self.mod_bitcell()
 
         self.inv = pinv()
         self.add_mod(self.inv)
@@ -134,12 +130,8 @@ class wordline_driver(design.design):
         inv2_xoffset = nand2_xoffset + self.nand2.width
         
         self.width = inv2_xoffset + self.inv.height
-        if self.bitcell.height > self.inv.height:
-            self.height = self.bitcell.height * self.rows
-            driver_height = self.bitcell.height
-        else:
-            self.height = self.inv.height * self.rows
-            driver_height = self.inv.height
+        driver_height = self.inv.height
+        self.height = self.inv.height * self.rows
         
         for row in range(self.rows):
             if (row % 2):

compiler/options.py

@@ -50,6 +50,8 @@ class options(optparse.Values):
     analytical_delay = True
     # Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
     purge_temp = True
+    # Determines whether multi-port portion of unit tests are run or not
+    multiport_check = True
 
     # These are the configuration parameters
     num_rw_ports = 1
@@ -69,8 +71,7 @@ class options(optparse.Values):
 
     # These are the default modules that can be over-riden
     decoder = "hierarchical_decoder"
-    ms_flop = "ms_flop"
-    ms_flop_array = "ms_flop_array"
+    dff_array = "dff_array"
     dff = "dff"
     control_logic = "control_logic"
     bitcell_array = "bitcell_array"

compiler/pgates/pbitcell.py

@@ -17,6 +17,7 @@ class pbitcell(design.design):
         self.num_rw_ports = OPTS.num_rw_ports
         self.num_w_ports = OPTS.num_w_ports
         self.num_r_ports = OPTS.num_r_ports
+        self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
         
         name = "pbitcell_{0}RW_{1}W_{2}R".format(self.num_rw_ports, self.num_w_ports, self.num_r_ports)
         # This is not a pgate because pgates depend on the bitcell height!
@@ -53,38 +54,79 @@ class pbitcell(design.design):
         
         if(self.num_rw_ports > 0):
             self.place_readwrite_ports()
+            self.route_readwrite_wordlines()
+            self.route_readwrite_bitlines()
+            if(self.num_w_ports == 0): # routing for write to storage is the same as read/write to storage
+                self.route_readwrite_access()
         if(self.num_w_ports > 0):
             self.place_write_ports()
+            self.route_write_wordlines()
+            self.route_write_bitlines()
+            self.route_write_access()
         if(self.num_r_ports > 0):
             self.place_read_ports()
+            self.route_read_wordlines()
+            self.route_read_bitlines()
+            self.route_read_access()
         self.extend_well()
         
         self.offset_all_coordinates()
         self.DRC_LVS()
     
     def add_pins(self):
+        self.rw_bl_names = []
+        self.rw_br_names = []
+        self.w_bl_names = []
+        self.w_br_names = []
+        self.r_bl_names = []
+        self.r_br_names = []
+        self.rw_wl_names = []
+        self.w_wl_names = []
+        self.r_wl_names = []
+        port = 0
+    
         for k in range(self.num_rw_ports):
-            self.add_pin("rwbl{}".format(k))
-            self.add_pin("rwbl_bar{}".format(k))
+            self.add_pin("bl{}".format(port))
+            self.add_pin("br{}".format(port))
+            self.rw_bl_names.append("bl{}".format(port))
+            self.rw_br_names.append("br{}".format(port))
+            port += 1
         for k in range(self.num_w_ports):
-            self.add_pin("wbl{}".format(k))
-            self.add_pin("wbl_bar{}".format(k))
+            self.add_pin("bl{}".format(port))
+            self.add_pin("br{}".format(port))
+            self.w_bl_names.append("bl{}".format(port))
+            self.w_br_names.append("br{}".format(port))
+            port += 1
         for k in range(self.num_r_ports):
-            self.add_pin("rbl{}".format(k))
-            self.add_pin("rbl_bar{}".format(k))
+            self.add_pin("bl{}".format(port))
+            self.add_pin("br{}".format(port))
+            self.r_bl_names.append("bl{}".format(port))
+            self.r_br_names.append("br{}".format(port))
+            port += 1
         
+        port = 0
         for k in range(self.num_rw_ports):
-            self.add_pin("rwwl{}".format(k))
+            self.add_pin("wl{}".format(port))
+            self.rw_wl_names.append("wl{}".format(port))
+            port += 1
         for k in range(self.num_w_ports):
-            self.add_pin("wwl{}".format(k))
+            self.add_pin("wl{}".format(port))
+            self.w_wl_names.append("wl{}".format(port))
+            port += 1
         for k in range(self.num_r_ports):
-            self.add_pin("rwl{}".format(k))
+            self.add_pin("wl{}".format(port))
+            self.r_wl_names.append("wl{}".format(port))
+            port += 1
             
         self.add_pin("vdd")
         self.add_pin("gnd")
+        
     
     def add_modules(self):
-        # if there are any read/write ports, then the inverter nmos is sized based the number of them
+        """
+        Determine size of transistors and add ptx modules
+        """
+        # if there are any read/write ports, then the inverter nmos is sized based the number of read/write ports
         if(self.num_rw_ports > 0):
             inverter_nmos_width = self.num_rw_ports*3*parameter["min_tx_size"]
             inverter_pmos_width = parameter["min_tx_size"]
@@ -92,7 +134,7 @@ class pbitcell(design.design):
             write_nmos_width = parameter["min_tx_size"]
             read_nmos_width = 2*parameter["min_tx_size"]
         
-        # if there are no read/write ports, then the inverter nmos is sized for the dual port case
+        # if there are no read/write ports, then the inverter nmos is statically sized for the dual port case
         else:
             inverter_nmos_width = 2*parameter["min_tx_size"]
             inverter_pmos_width = parameter["min_tx_size"]
@@ -100,7 +142,6 @@ class pbitcell(design.design):
             write_nmos_width = parameter["min_tx_size"]
             read_nmos_width = 2*parameter["min_tx_size"]
     
-        """ Create ptx for all transistors """
         # create ptx for inverter transistors
         self.inverter_nmos = ptx(width=inverter_nmos_width,
                                  tx_type="nmos")
@@ -180,17 +221,17 @@ class pbitcell(design.design):
             
         self.write_to_read_spacing = write_portion + read_portion + 2*contact.poly.width + drc["poly_to_polycontact"]
         
-        """ calculations for transistor tiling (transistor + spacing) """
+        # calculations for transistor tiling (transistor + spacing)
         self.inverter_tile_width = self.inverter_nmos.active_width + 0.5*self.inverter_to_inverter_spacing
         self.readwrite_tile_width = self.readwrite_to_readwrite_spacing + self.readwrite_nmos.active_height
         self.write_tile_width = self.write_to_write_spacing + self.write_nmos.active_height
         self.read_tile_width = self.read_to_read_spacing + self.read_nmos.active_height
         
-        """ calculation for row line tiling """
-        self.rail_tile_height = drc["active_to_body_active"] + contact.well.width #0.5*(drc["minwidth_tx"] - drc["minwidth_metal1"]) + drc["minwidth_metal1"]
+        # calculation for row line tiling
+        self.rail_tile_height = drc["active_to_body_active"] + contact.well.width
         self.rowline_tile_height = drc["minwidth_metal1"] + contact.m1m2.width
         
-        """ calculations related to inverter connections """
+        # calculations related to inverter connections
         self.inverter_gap = drc["poly_to_active"] + drc["poly_to_polycontact"] + 2*contact.poly.width + drc["minwidth_metal1"] + self.inverter_pmos_contact_extension
         self.cross_couple_lower_ypos = self.inverter_nmos.active_height + drc["poly_to_active"] + 0.5*contact.poly.width
         self.cross_couple_upper_ypos = self.inverter_nmos.active_height + drc["poly_to_active"] + drc["poly_to_polycontact"] + 1.5*contact.poly.width
@@ -198,7 +239,7 @@ class pbitcell(design.design):
     
     def calculate_postions(self):
         """ 
-        Calculate positions that describe the edges of the cell 
+        Calculate positions that describe the edges and dimensions of the cell 
         """
         # create flags for excluding readwrite, write, or read port calculations if they are not included in the bitcell
         if(self.num_rw_ports > 0):
@@ -286,8 +327,7 @@ class pbitcell(design.design):
         
     def place_storage(self):
         """
-        Places the crossed coupled inverters that act as storage for the bitcell.
-        The stored value of the cell is denoted as "Q", and the inverted value as "Q_bar".
+        Places the transistors for the crossed coupled inverters in the bitcell
         """
         
         # calculate transistor offsets
@@ -304,7 +344,9 @@ class pbitcell(design.design):
         self.inverter_pmos_right.place([right_inverter_xpos, inverter_pmos_ypos])
 
     def route_storage(self):
-        
+        """
+        Routes inputs and outputs of inverters to cross couple them
+        """
         # connect input (gate) of inverters
         self.add_path("poly", [self.inverter_nmos_left.get_pin("G").uc(), self.inverter_pmos_left.get_pin("G").bc()])
         self.add_path("poly", [self.inverter_nmos_right.get_pin("G").uc(), self.inverter_pmos_right.get_pin("G").bc()]) 
@@ -338,9 +380,8 @@ class pbitcell(design.design):
         
     def route_rails(self):
         """
-        Add gnd and vdd rails and connects them to the inverters
+        Adds gnd and vdd rails and connects them to the inverters
         """
-        
         # Add rails for vdd and gnd
         self.gnd_position = vector(self.leftmost_xpos, -self.rail_tile_height)
         self.gnd = self.add_layout_pin(text="gnd",
@@ -393,11 +434,11 @@ class pbitcell(design.design):
             # add read/write transistors
             self.readwrite_nmos_left[k] = self.add_inst(name="readwrite_nmos_left{}".format(k),
                                                         mod=self.readwrite_nmos)
-            self.connect_inst(["Q", "rwwl{}".format(k), "rwbl{}".format(k), "gnd"])
+            self.connect_inst(["Q", self.rw_wl_names[k], self.rw_bl_names[k], "gnd"])
             
             self.readwrite_nmos_right[k] = self.add_inst(name="readwrite_nmos_right{}".format(k),
                                                          mod=self.readwrite_nmos)
-            self.connect_inst(["Q_bar", "rwwl{}".format(k), "rwbl_bar{}".format(k), "gnd"])
+            self.connect_inst(["Q_bar", self.rw_wl_names[k], self.rw_br_names[k], "gnd"])
                         
 
     def place_readwrite_ports(self):
@@ -440,46 +481,43 @@ class pbitcell(design.design):
             self.rwwl_positions[k] = vector(self.leftmost_xpos, rwwl_ypos)
             
             # add pin for RWWL
-            self.add_layout_pin(text="rwwl{}".format(k),
+            self.add_layout_pin(text=self.rw_wl_names[k],
                                 layer="metal1",
                                 offset=self.rwwl_positions[k],
                                 width=self.width,
                                 height=contact.m1m2.width)
-                       
-            # Source/RWBL/RWBL_bar connections 
-            # add metal1-to-metal2 contacts on top of read/write transistor source pins for connection to WBL and WBL_bar
-            offset_left = self.readwrite_nmos_left[k].get_pin("S").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_left,
-                                    rotate=90)
-            
-            offset_right = self.readwrite_nmos_right[k].get_pin("S").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_right,
-                                    rotate=90)
-            
+                      
             # add pins for RWBL and RWBL_bar, overlaid on source contacts
             self.rwbl_positions[k] = vector(self.readwrite_nmos_left[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="rwbl{}".format(k),
+            self.add_layout_pin(text=self.rw_bl_names[k],
                                 layer="metal2",
                                 offset=self.rwbl_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
 
             self.rwbl_bar_positions[k] = vector(self.readwrite_nmos_right[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="rwbl_bar{}".format(k),
+            self.add_layout_pin(text=self.rw_br_names[k],
                                 layer="metal2",
                                 offset=self.rwbl_bar_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
-                        
+        
+        # update furthest left and right transistor edges 
+        self.left_building_edge = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height
+        self.right_building_edge = right_readwrite_transistor_xpos
+        
+    def route_readwrite_wordlines(self):
+        """
+        Routes read/write trnasistors to their respective wordlines
+        """
+        for k in range(0,self.num_rw_ports):
             # Gate/RWWL connections 
             # add poly-to-meltal2 contacts to connect gate of read/write transistors to RWWL (contact next to gate)
             # contact must be placed a metal1 width below the source pin to avoid drc from source pin routings
             if(self.readwrite_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.readwrite_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width
             else:
-                contact_xpos = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
+                contact_xpos = self.readwrite_nmos_left[k].offset.x - self.readwrite_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
             contact_ypos = self.readwrite_nmos_left[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height
             left_gate_contact =  vector(contact_xpos, contact_ypos)
             
@@ -491,7 +529,7 @@ class pbitcell(design.design):
             if(self.readwrite_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.readwrite_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width
             else:
-                contact_xpos = right_readwrite_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width
+                contact_xpos = self.readwrite_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width
             contact_ypos = self.readwrite_nmos_right[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height
             right_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -521,45 +559,62 @@ class pbitcell(design.design):
             # connect read/write transistor gate contacts to RWWL contacts (metal2 path)
             self.add_path("metal2", [left_gate_contact, left_rwwl_contact])
             self.add_path("metal2", [right_gate_contact, right_rwwl_contact])
-                       
-            # Drain/Storage connections 
-            # this path only needs to be drawn once on the last iteration of the loop
-            if(k == self.num_rw_ports-1):
-                # add contacts to connect gate of inverters to drain of read/write transistors
-                left_storage_contact =  vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos)
-                self.add_contact_center(layers=("poly", "contact", "metal1"),
-                                                offset=left_storage_contact,
-                                                rotate=90)
-                
-                right_storage_contact =  vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos)
-                self.add_contact_center(layers=("poly", "contact", "metal1"),
-                                                offset=right_storage_contact,
-                                                rotate=90)
-                                 
-                # connect gate of inverters to contacts (poly path)
-                inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos)
-                self.add_path("poly", [left_storage_contact, inverter_gate_offset_left])
-                
-                inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos)
-                self.add_path("poly", [right_storage_contact, inverter_gate_offset_right])
-                
-                # connect contacts to drains of read/write transistors (metal1 path)
-                midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y)
-                midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.readwrite_nmos_left[k].get_pin("D").lc().y)
-                self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error
-                self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.readwrite_nmos_left[k].get_pin("D").lc()])
-                
-                midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y)
-                midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.readwrite_nmos_right[k].get_pin("D").rc().y)
-                self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width)
-                self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.readwrite_nmos_right[k].get_pin("D").rc()])
-            # end if
-        # end for
         
-        # update furthest left and right transistor edges 
-        self.left_building_edge = left_readwrite_transistor_xpos - self.readwrite_nmos.active_height
-        self.right_building_edge = right_readwrite_transistor_xpos
         
+    def route_readwrite_bitlines(self):
+        """ 
+        Routes read/write transistors to their respective bitlines
+        """
+        for k in range(0,self.num_rw_ports):
+            # Source/RWBL/RWBL_bar connections 
+            # add metal1-to-metal2 contacts on top of read/write transistor source pins for connection to WBL and WBL_bar
+            offset_left = self.readwrite_nmos_left[k].get_pin("S").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_left,
+                                    rotate=90)
+            
+            offset_right = self.readwrite_nmos_right[k].get_pin("S").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_right,
+                                    rotate=90)
+        
+        
+    def route_readwrite_access(self):
+        """
+        Routes read/write transistors to the storage component of the bitcell
+        """
+        last_inst = self.num_rw_ports - 1
+    
+        # Drain/Storage connections 
+        # this path only needs to be drawn once on the last iteration of the loop
+        # add contacts to connect gate of inverters to drain of read/write transistors
+        left_storage_contact =  vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos)
+        self.add_contact_center(layers=("poly", "contact", "metal1"),
+                                        offset=left_storage_contact,
+                                        rotate=90)
+        
+        right_storage_contact =  vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos)
+        self.add_contact_center(layers=("poly", "contact", "metal1"),
+                                        offset=right_storage_contact,
+                                        rotate=90)
+                         
+        # connect gate of inverters to contacts (poly path)
+        inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos)
+        self.add_path("poly", [left_storage_contact, inverter_gate_offset_left])
+        
+        inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos)
+        self.add_path("poly", [right_storage_contact, inverter_gate_offset_right])
+        
+        # connect contacts to drains of read/write transistors (metal1 path)
+        midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y)
+        midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.readwrite_nmos_left[last_inst].get_pin("D").lc().y)
+        self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error
+        self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.readwrite_nmos_left[last_inst].get_pin("D").lc()])
+        
+        midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y)
+        midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.readwrite_nmos_right[last_inst].get_pin("D").rc().y)
+        self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width)
+        self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.readwrite_nmos_right[last_inst].get_pin("D").rc()])
     
     def create_write_ports(self):
         """
@@ -583,18 +638,17 @@ class pbitcell(design.design):
             # add write transistors
             self.write_nmos_left[k] = self.add_inst(name="write_nmos_left{}".format(k),
                                                     mod=self.write_nmos)
-            self.connect_inst(["Q", "wwl{}".format(k), "wbl{}".format(k), "gnd"])
+            self.connect_inst(["Q", self.w_wl_names[k], self.w_bl_names[k], "gnd"])
             
             self.write_nmos_right[k] = self.add_inst(name="write_nmos_right{}".format(k),
                                                      mod=self.write_nmos)
-            self.connect_inst(["Q_bar", "wwl{}".format(k), "wbl_bar{}".format(k), "gnd"])
+            self.connect_inst(["Q_bar", self.w_wl_names[k], self.w_br_names[k], "gnd"])
                         
 
     def place_write_ports(self):
         """
         Places write ports in the bit cell. 
         """
-    
         # Define variables relevant to write transistors 
         self.wwl_positions = [None] * self.num_w_ports
         self.wbl_positions = [None] * self.num_w_ports
@@ -634,46 +688,43 @@ class pbitcell(design.design):
             self.wwl_positions[k] = vector(self.leftmost_xpos, wwl_ypos)
             
             # add pin for WWL
-            self.add_layout_pin(text="wwl{}".format(k),
+            self.add_layout_pin(text=self.w_wl_names[k],
                                 layer="metal1",
                                 offset=self.wwl_positions[k],
                                 width=self.width,
                                 height=contact.m1m2.width)
                        
-            # Source/WBL/WBL_bar connections 
-            # add metal1-to-metal2 contacts on top of write transistor source pins for connection to WBL and WBL_bar
-            offset_left = self.write_nmos_left[k].get_pin("S").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_left,
-                                    rotate=90)
-            
-            offset_right = self.write_nmos_right[k].get_pin("S").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_right,
-                                    rotate=90)
-            
             # add pins for WBL and WBL_bar, overlaid on source contacts
             self.wbl_positions[k] = vector(self.write_nmos_left[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="wbl{}".format(k),
+            self.add_layout_pin(text=self.w_bl_names[k],
                                 layer="metal2",
                                 offset=self.wbl_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
 
             self.wbl_bar_positions[k] = vector(self.write_nmos_right[k].get_pin("S").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="wbl_bar{}".format(k),
+            self.add_layout_pin(text=self.w_br_names[k],
                                 layer="metal2",
                                 offset=self.wbl_bar_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
-                        
+        
+        # update furthest left and right transistor edges 
+        self.left_building_edge = left_write_transistor_xpos - self.write_nmos.active_height
+        self.right_building_edge = right_write_transistor_xpos
+        
+    def route_write_wordlines(self):
+        """
+        Routes write transistors to their respective wordlines
+        """
+        for k in range(0,self.num_w_ports):
             # Gate/WWL connections
             # add poly-to-meltal2 contacts to connect gate of write transistors to WWL (contact next to gate)
             # contact must be placed a metal width below the source pin to avoid drc from source pin routings
             if(self.write_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.write_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width
             else:
-                contact_xpos = left_write_transistor_xpos - self.write_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
+                contact_xpos = self.write_nmos_left[k].offset.x - self.write_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
             contact_ypos = self.write_nmos_left[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height
             left_gate_contact =  vector(contact_xpos, contact_ypos)
             
@@ -685,7 +736,7 @@ class pbitcell(design.design):
             if(self.write_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.write_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width
             else:
-                contact_xpos = right_write_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width
+                contact_xpos = self.write_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width
             contact_ypos = self.write_nmos_right[k].get_pin("D").bc().y - drc["minwidth_metal1"] - 0.5*contact.m1m2.height
             right_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -715,42 +766,60 @@ class pbitcell(design.design):
             # connect write transistor gate contacts to WWL contacts (metal2 path)
             self.add_path("metal2", [left_gate_contact, left_wwl_contact])
             self.add_path("metal2", [right_gate_contact, right_wwl_contact])
-                       
-            # Drain/Storage connections 
-            # this path only needs to be drawn once on the last iteration of the loop
-            if(k == self.num_w_ports-1):
-                # add contacts to connect gate of inverters to drain of write transistors
-                left_storage_contact =  vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos)
-                self.add_contact_center(layers=("poly", "contact", "metal1"),
-                                                offset=left_storage_contact,
-                                                rotate=90)
+    
+    def route_write_bitlines(self):
+        """
+        Routes write transistors to their respective bitlines
+        """
+        for k in range(0,self.num_w_ports):
+            # Source/WBL/WBL_bar connections 
+            # add metal1-to-metal2 contacts on top of write transistor source pins for connection to WBL and WBL_bar
+            offset_left = self.write_nmos_left[k].get_pin("S").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_left,
+                                    rotate=90)
+            
+            offset_right = self.write_nmos_right[k].get_pin("S").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_right,
+                                    rotate=90)
                 
-                right_storage_contact =  vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos)
-                self.add_contact_center(layers=("poly", "contact", "metal1"),
-                                                offset=right_storage_contact,
-                                                rotate=90)
-                                 
-                # connect gate of inverters to contacts (poly path)
-                inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos)
-                self.add_path("poly", [left_storage_contact, inverter_gate_offset_left])
-                
-                inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos)
-                self.add_path("poly", [right_storage_contact, inverter_gate_offset_right])
-                
-                # connect contacts to drains of write transistors (metal1 path)
-                midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y)
-                midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.write_nmos_left[k].get_pin("D").lc().y)
-                self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error
-                self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.write_nmos_left[k].get_pin("D").lc()])
-                
-                midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y)
-                midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.write_nmos_right[k].get_pin("D").rc().y)
-                self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width)
-                self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.write_nmos_right[k].get_pin("D").rc()])
+    def route_write_access(self):
+        """ 
+        Routes write transistors to the storage component of the bitcell
+        """
+        last_inst = self.num_w_ports - 1
+    
+        # Drain/Storage connections 
+        # this path only needs to be drawn once on the last iteration of the loop
+        # add contacts to connect gate of inverters to drain of write transistors
+        left_storage_contact =  vector(self.inverter_nmos_left.get_pin("G").lc().x - drc["poly_to_polycontact"] - 0.5*contact.poly.width, self.cross_couple_lower_ypos)
+        self.add_contact_center(layers=("poly", "contact", "metal1"),
+                                        offset=left_storage_contact,
+                                        rotate=90)
         
-        # update furthest left and right transistor edges 
-        self.left_building_edge = left_write_transistor_xpos - self.write_nmos.active_height
-        self.right_building_edge = right_write_transistor_xpos
+        right_storage_contact =  vector(self.inverter_nmos_right.get_pin("G").rc().x + drc["poly_to_polycontact"] + 0.5*contact.poly.width, self.cross_couple_lower_ypos)
+        self.add_contact_center(layers=("poly", "contact", "metal1"),
+                                        offset=right_storage_contact,
+                                        rotate=90)
+                         
+        # connect gate of inverters to contacts (poly path)
+        inverter_gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").lc().x, self.cross_couple_lower_ypos)
+        self.add_path("poly", [left_storage_contact, inverter_gate_offset_left])
+        
+        inverter_gate_offset_right = vector(self.inverter_nmos_right.get_pin("G").rc().x, self.cross_couple_lower_ypos)
+        self.add_path("poly", [right_storage_contact, inverter_gate_offset_right])
+        
+        # connect contacts to drains of write transistors (metal1 path)
+        midL0 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], left_storage_contact.y)
+        midL1 = vector(self.inverter_nmos_left.get_pin("S").lc().x - 1.5*drc["minwidth_metal1"], self.write_nmos_left[last_inst].get_pin("D").lc().y)
+        self.add_path("metal1", [left_storage_contact, midL0], width=contact.poly.second_layer_width) # width needed to avoid drc error
+        self.add_path("metal1", [midL0+vector(0,0.5*contact.poly.second_layer_width), midL1, self.write_nmos_left[last_inst].get_pin("D").lc()])
+        
+        midR0 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], right_storage_contact.y)
+        midR1 = vector(self.inverter_nmos_right.get_pin("D").rc().x + 1.5*drc["minwidth_metal1"], self.write_nmos_right[last_inst].get_pin("D").rc().y)
+        self.add_path("metal1", [right_storage_contact, midR0], width=contact.poly.second_layer_width)
+        self.add_path("metal1", [midR0+vector(0,0.5*contact.poly.second_layer_width), midR1, self.write_nmos_right[last_inst].get_pin("D").rc()])
 
                 
     def create_read_ports(self):
@@ -785,17 +854,16 @@ class pbitcell(design.design):
             # add read transistors
             self.read_nmos_left[k] = self.add_inst(name="read_nmos_left{}".format(k),
                                                    mod=self.read_nmos)
-            self.connect_inst(["rbl{}".format(k), "rwl{}".format(k), "RA_to_R_left{}".format(k), "gnd"])
+            self.connect_inst([self.r_bl_names[k], self.r_wl_names[k], "RA_to_R_left{}".format(k), "gnd"])
             
             self.read_nmos_right[k] = self.add_inst(name="read_nmos_right{}".format(k),
                                                     mod=self.read_nmos)
-            self.connect_inst(["rbl_bar{}".format(k), "rwl{}".format(k), "RA_to_R_right{}".format(k), "gnd"])
+            self.connect_inst([self.r_br_names[k], self.r_wl_names[k], "RA_to_R_right{}".format(k), "gnd"])
                         
     def place_read_ports(self):
         """
         Places the read ports in the bit cell. 
         """
-        
         # Define variables relevant to read transistors
         self.rwl_positions = [None] * self.num_r_ports
         self.rbl_positions = [None] * self.num_r_ports
@@ -844,45 +912,38 @@ class pbitcell(design.design):
             self.rwl_positions[k] = vector(self.leftmost_xpos, rwl_ypos)
             
             # add pin for RWL
-            self.add_layout_pin(text="rwl{}".format(k),
+            self.add_layout_pin(text=self.r_wl_names[k],
                                 layer="metal1",
                                 offset=self.rwl_positions[k],
                                 width=self.width,
                                 height=contact.m1m2.width)
-                       
-            # Drain of read transistor / RBL & RBL_bar connection 
-            # add metal1-to-metal2 contacts on top of read transistor drain pins for connection to RBL and RBL_bar
-            offset_left = self.read_nmos_left[k].get_pin("D").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_left,
-                                    rotate=90)
-            
-            offset_right = self.read_nmos_right[k].get_pin("D").center()
-            self.add_contact_center(layers=("metal1", "via1", "metal2"),
-                                    offset=offset_right,
-                                    rotate=90)
             
             # add pins for RBL and RBL_bar, overlaid on drain contacts
             self.rbl_positions[k] = vector(self.read_nmos_left[k].get_pin("D").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="rbl{}".format(k),
+            self.add_layout_pin(text=self.r_bl_names[k],
                                 layer="metal2",
                                 offset=self.rbl_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
 
             self.rbl_bar_positions[k] = vector(self.read_nmos_right[k].get_pin("D").center().x - 0.5*drc["minwidth_metal2"], self.botmost_ypos)
-            self.add_layout_pin(text="rbl_bar{}".format(k),
+            self.add_layout_pin(text=self.r_br_names[k],
                                 layer="metal2",
                                 offset=self.rbl_bar_positions[k],
                                 width=drc["minwidth_metal2"],
                                 height=self.height)
-                       
+        
+    def route_read_wordlines(self):
+        """
+        Routes read transistors to their respective worlines
+        """
+        for k in range(0,self.num_r_ports):
             # Gate of read transistor / RWL connection 
             # add poly-to-meltal2 contacts to connect gate of read transistors to RWL (contact next to gate)
             if(self.read_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.read_nmos_left[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width
             else:
-                contact_xpos = left_read_transistor_xpos - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
+                contact_xpos = self.read_nmos_left[k].offset.x - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
             contact_ypos = self.read_nmos_left[k].get_pin("G").lc().y
             left_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -894,7 +955,7 @@ class pbitcell(design.design):
             if(self.read_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.read_nmos_right[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width
             else:
-                contact_xpos = right_read_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width
+                contact_xpos = self.read_nmos_right[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width
             contact_ypos = self.read_nmos_right[k].get_pin("G").rc().y
             right_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -929,13 +990,35 @@ class pbitcell(design.design):
             
             gnd_offset_right = vector(self.read_access_nmos_right[k].get_pin("S").bc().x, self.gnd_position.y)
             self.add_path("metal1", [self.read_access_nmos_right[k].get_pin("S").bc(), gnd_offset_right])
+    
+    def route_read_bitlines(self):
+        """
+        Routes read transistors to their respective bitlines
+        """
+        for k in range(0,self.num_r_ports):
+            # Drain of read transistor / RBL & RBL_bar connection 
+            # add metal1-to-metal2 contacts on top of read transistor drain pins for connection to RBL and RBL_bar
+            offset_left = self.read_nmos_left[k].get_pin("D").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_left,
+                                    rotate=90)
             
+            offset_right = self.read_nmos_right[k].get_pin("D").center()
+            self.add_contact_center(layers=("metal1", "via1", "metal2"),
+                                    offset=offset_right,
+                                    rotate=90)  
+    
+    def route_read_access(self):
+        """ 
+        Routes read access transistors to the storage component of the bitcell
+        """
+        for k in range(0,self.num_r_ports):
             # Gate of read-access transistor / storage connection 
             # add poly-to-metal1 contacts to connect gate of read-access transistors to output of inverters (contact next to gate)
             if(self.read_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.read_nmos_left[k].get_pin("S").rc().x + drc["minwidth_metal2"] + 0.5*contact.m1m2.width
             else:
-                contact_xpos = left_read_transistor_xpos + drc["poly_to_active"] + 0.5*contact.poly.width
+                contact_xpos = self.read_nmos_left[k].offset.x + drc["poly_to_active"] + 0.5*contact.poly.width
             contact_ypos = self.read_access_nmos_left[k].get_pin("G").rc().y
             left_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -945,7 +1028,7 @@ class pbitcell(design.design):
             if(self.read_nmos_contact_extension > self.gate_contact_thres):
                 contact_xpos = self.read_nmos_right[k].get_pin("S").lc().x - drc["minwidth_metal2"] - 0.5*contact.m1m2.width
             else:
-                contact_xpos = right_read_transistor_xpos - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
+                contact_xpos = self.read_nmos_right[k].offset.x - self.read_nmos.active_height - drc["poly_to_active"] - 0.5*contact.poly.width
             contact_ypos = self.read_access_nmos_right[k].get_pin("G").lc().y
             right_gate_contact = vector(contact_xpos, contact_ypos)
             
@@ -977,8 +1060,6 @@ class pbitcell(design.design):
             midR2 = vector(right_gate_contact0.x, self.cross_couple_upper_ypos)
             right_inverter_offset = vector(self.inverter_nmos_right.get_pin("S").center().x, self.cross_couple_upper_ypos)
             self.add_path("metal1", [right_gate_contact, midR0, midR1, midR2, right_inverter_offset])
-        # end for
-            
         
     def extend_well(self):
         """
@@ -1083,134 +1164,54 @@ class pbitcell(design.design):
     def list_bitcell_pins(self, col, row):
         """ Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
         bitcell_pins = []
-        for k in range(self.num_rw_ports):
-            bitcell_pins.append("rwbl{0}[{1}]".format(k,col))
-            bitcell_pins.append("rwbl_bar{0}[{1}]".format(k,col))
-        for k in range(self.num_w_ports):
-            bitcell_pins.append("wbl{0}[{1}]".format(k,col))
-            bitcell_pins.append("wbl_bar{0}[{1}]".format(k,col))
-        for k in range(self.num_r_ports):
-            bitcell_pins.append("rbl{0}[{1}]".format(k,col))
-            bitcell_pins.append("rbl_bar{0}[{1}]".format(k,col))
-        for k in range(self.num_rw_ports):
-            bitcell_pins.append("rwwl{0}[{1}]".format(k,row))
-        for k in range(self.num_w_ports):
-            bitcell_pins.append("wwl{0}[{1}]".format(k,row))
-        for k in range(self.num_r_ports):
-            bitcell_pins.append("rwl{0}[{1}]".format(k,row))
+        for port in range(self.total_ports):
+            bitcell_pins.append("bl{0}[{1}]".format(port,col))
+            bitcell_pins.append("br{0}[{1}]".format(port,col))
+        for port in range(self.total_ports):
+            bitcell_pins.append("wl{0}[{1}]".format(port,row))
         bitcell_pins.append("vdd")
         bitcell_pins.append("gnd")
-        
         return bitcell_pins
     
     def list_all_wl_names(self):
         """ Creates a list of all wordline pin names """
-        row_pins = []
-        for k in range(self.num_rw_ports):
-            row_pins.append("rwwl{0}".format(k))
-        for k in range(self.num_w_ports):
-            row_pins.append("wwl{0}".format(k))
-        for k in range(self.num_r_ports):
-            row_pins.append("rwl{0}".format(k))
-            
-        return row_pins
-    
-    def list_read_wl_names(self):
-        """ Creates a list of wordline pin names associated with read ports """
-        row_pins = []
-        for k in range(self.num_rw_ports):
-            row_pins.append("rwwl{0}".format(k))
-        for k in range(self.num_r_ports):
-            row_pins.append("rwl{0}".format(k))
-            
-        return row_pins
-    
-    def list_write_wl_names(self):
-        """ Creates a list of wordline pin names associated with write ports """
-        row_pins = []
-        for k in range(self.num_rw_ports):
-            row_pins.append("rwwl{0}".format(k))
-        for k in range(self.num_w_ports):
-            row_pins.append("wwl{0}".format(k))
-            
-        return row_pins
-    
+        wordline_names = self.rw_wl_names + self.w_wl_names + self.r_wl_names
+        return wordline_names
     
     def list_all_bitline_names(self):
         """ Creates a list of all bitline pin names (both bl and br) """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl{0}".format(k))
-            column_pins.append("rwbl_bar{0}".format(k))
-        for k in range(self.num_w_ports):
-            column_pins.append("wbl{0}".format(k))
-            column_pins.append("wbl_bar{0}".format(k))
-        for k in range(self.num_r_ports):
-            column_pins.append("rbl{0}".format(k))
-            column_pins.append("rbl_bar{0}".format(k))
-            
-        return column_pins
+        bitline_pins = []
+        for port in range(self.total_ports):
+            bitline_pins.append("bl{0}".format(port))
+            bitline_pins.append("br{0}".format(port))
+        return bitline_pins
         
     def list_all_bl_names(self):
         """ Creates a list of all bl pins names """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl{0}".format(k))
-        for k in range(self.num_w_ports):
-            column_pins.append("wbl{0}".format(k))
-        for k in range(self.num_r_ports):
-            column_pins.append("rbl{0}".format(k))
-            
-        return column_pins
+        bl_pins = self.rw_bl_names + self.w_bl_names + self.r_bl_names    
+        return bl_pins
         
     def list_all_br_names(self):
         """ Creates a list of all br pins names """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl_bar{0}".format(k))
-        for k in range(self.num_w_ports):
-            column_pins.append("wbl_bar{0}".format(k))
-        for k in range(self.num_r_ports):
-            column_pins.append("rbl_bar{0}".format(k))
-            
-        return column_pins
+        br_pins = self.rw_br_names + self.w_br_names + self.r_br_names     
+        return br_pins
         
     def list_read_bl_names(self):
         """ Creates a list of bl pin names associated with read ports """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl{0}".format(k))
-        for k in range(self.num_r_ports):
-            column_pins.append("rbl{0}".format(k))
-            
-        return column_pins
+        bl_pins = self.rw_bl_names + self.r_bl_names     
+        return bl_pins
         
     def list_read_br_names(self):
         """ Creates a list of br pin names associated with read ports """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl_bar{0}".format(k))
-        for k in range(self.num_r_ports):
-            column_pins.append("rbl_bar{0}".format(k))
-            
-        return column_pins
+        br_pins = self.rw_br_names + self.r_br_names     
+        return br_pins
         
     def list_write_bl_names(self):
         """ Creates a list of bl pin names associated with write ports """
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl{0}".format(k))
-        for k in range(self.num_w_ports):
-            column_pins.append("wbl{0}".format(k))
-            
-        return column_pins
+        bl_pins = self.rw_bl_names + self.w_bl_names  
+        return bl_pins
     
     def list_write_br_names(self):
         """ Creates a list of br pin names asscociated with write ports"""
-        column_pins = []
-        for k in range(self.num_rw_ports):
-            column_pins.append("rwbl_bar{0}".format(k))
-        for k in range(self.num_w_ports):
-            column_pins.append("wbl_bar{0}".format(k))
-            
-        return column_pins
+        br_pins = self.rw_br_names + self.w_br_names  
+        return br_pins

compiler/pgates/pinv.py

@@ -279,5 +279,5 @@ class pinv(pgate.pgate):
         """Computes effective capacitance. Results in fF"""
         c_load = load
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
-        transistion_prob = spice["inv_transisition_prob"]
-        return transistion_prob*(c_load + c_para) 
+        transition_prob = spice["inv_transition_prob"]
+        return transition_prob*(c_load + c_para) 

compiler/pgates/pnand2.py

@@ -240,5 +240,5 @@ class pnand2(pgate.pgate):
         """Computes effective capacitance. Results in fF"""
         c_load = load
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
-        transistion_prob = spice["nand2_transisition_prob"]
-        return transistion_prob*(c_load + c_para) 
+        transition_prob = spice["nand2_transition_prob"]
+        return transition_prob*(c_load + c_para) 

compiler/pgates/pnand3.py

@@ -259,5 +259,5 @@ class pnand3(pgate.pgate):
         """Computes effective capacitance. Results in fF"""
         c_load = load
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
-        transistion_prob = spice["nand3_transisition_prob"]
-        return transistion_prob*(c_load + c_para) 
+        transition_prob = spice["nand3_transition_prob"]
+        return transition_prob*(c_load + c_para) 

compiler/pgates/pnor2.py

@@ -237,6 +237,6 @@ class pnor2(pgate.pgate):
         """Computes effective capacitance. Results in fF"""
         c_load = load
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
-        transistion_prob = spice["nor2_transisition_prob"]
-        return transistion_prob*(c_load + c_para) 
+        transition_prob = spice["nor2_transition_prob"]
+        return transition_prob*(c_load + c_para) 
         

compiler/pgates/single_level_column_mux.py

@@ -12,12 +12,17 @@ class single_level_column_mux(design.design):
     Creates a single columnmux cell.
     """
 
-    def __init__(self, tx_size):
-        name="single_level_column_mux_{}".format(tx_size)
+    unique_id = 1
+    
+    def __init__(self, tx_size, bitcell_bl="bl", bitcell_br="br"):
+        name="single_level_column_mux_{}_no{}".format(tx_size,single_level_column_mux.unique_id)
+        single_level_column_mux.unique_id += 1
         design.design.__init__(self, name)
         debug.info(2, "create single column mux cell: {0}".format(name))
 
         self.tx_size = tx_size
+        self.bitcell_bl = bitcell_bl
+        self.bitcell_br = bitcell_br
         
         self.create_netlist()
         if not OPTS.netlist_only:
@@ -59,8 +64,8 @@ class single_level_column_mux(design.design):
     def add_bitline_pins(self):
         """ Add the top and bottom pins to this cell """
 
-        bl_pos = vector(self.bitcell.get_pin("bl").lx(), 0)
-        br_pos = vector(self.bitcell.get_pin("br").lx(), 0)
+        bl_pos = vector(self.bitcell.get_pin(self.bitcell_bl).lx(), 0)
+        br_pos = vector(self.bitcell.get_pin(self.bitcell_br).lx(), 0)
 
         # bl and br
         self.add_layout_pin(text="bl",

compiler/sram_1bank.py

@@ -34,7 +34,9 @@ class sram_1bank(sram_base):
         
         self.bank_inst=self.create_bank(0)
 
-        self.control_logic_inst = self.create_control_logic()
+        self.control_logic_inst = [None] * self.total_ports
+        for port in range(self.total_ports):
+            self.control_logic_inst[port] = self.create_control_logic(port)
 
         self.row_addr_dff_inst = self.create_row_addr_dff()
 
@@ -59,11 +61,11 @@ class sram_1bank(sram_base):
         # up to the row address DFFs.
         control_pos = vector(-self.control_logic.width - 2*self.m2_pitch,
                              self.bank.bank_center.y - self.control_logic.control_logic_center.y)
-        self.control_logic_inst.place(control_pos)
+        self.control_logic_inst[0].place(control_pos)
 
         # The row address bits are placed above the control logic aligned on the right.
-        row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width,
-                              self.control_logic_inst.uy())
+        row_addr_pos = vector(self.control_logic_inst[0].rx() - self.row_addr_dff.width,
+                              self.control_logic_inst[0].uy())
         self.row_addr_dff_inst.place(row_addr_pos)
 
         # This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
@@ -95,7 +97,7 @@ class sram_1bank(sram_base):
         """
         # Connect the control pins as inputs
         for n in self.control_logic_inputs + ["clk"]:
-            self.copy_layout_pin(self.control_logic_inst, n)
+            self.copy_layout_pin(self.control_logic_inst[0], n)
 
         for i in range(self.word_size):
             dout_name = "dout0[{}]".format(i)
@@ -134,7 +136,7 @@ class sram_1bank(sram_base):
         """ Route the clock network """
 
         # This is the actual input to the SRAM
-        self.copy_layout_pin(self.control_logic_inst, "clk")
+        self.copy_layout_pin(self.control_logic_inst[0], "clk")
 
         # Connect all of these clock pins to the clock in the central bus
         # This is something like a "spine" clock distribution. The two spines
@@ -158,7 +160,7 @@ class sram_1bank(sram_base):
 
         # This uses a metal2 track to the right of the control/row addr DFF
         # to route vertically.
-        control_clk_buf_pin = self.control_logic_inst.get_pin("clk_buf")
+        control_clk_buf_pin = self.control_logic_inst[0].get_pin("clk_buf")
         control_clk_buf_pos = control_clk_buf_pin.rc()
         row_addr_clk_pin = self.row_addr_dff_inst.get_pin("clk")
         row_addr_clk_pos = row_addr_clk_pin.rc()
@@ -177,7 +179,7 @@ class sram_1bank(sram_base):
         top_instances = [self.bank_inst,
                          self.row_addr_dff_inst,
                          self.data_dff_inst,
-                         self.control_logic_inst]
+                         self.control_logic_inst[0]]
         if self.col_addr_dff:
             top_instances.append(self.col_addr_dff_inst)
 
@@ -193,7 +195,7 @@ class sram_1bank(sram_base):
         top_instances = [self.bank_inst,
                          self.row_addr_dff_inst,
                          self.data_dff_inst,
-                         self.control_logic_inst]
+                         self.control_logic_inst[0]]
         if self.col_addr_dff:
             top_instances.append(self.col_addr_dff_inst)
 
@@ -267,7 +269,7 @@ class sram_1bank(sram_base):
     def route_control_logic(self):
         """ Route the outputs from the control logic module """
         for n in self.control_logic_outputs:
-            src_pin = self.control_logic_inst.get_pin(n)
+            src_pin = self.control_logic_inst[0].get_pin(n)
             dest_pin = self.bank_inst.get_pin(n)                
             self.connect_rail_from_left_m2m3(src_pin, dest_pin)
             self.add_via_center(layers=("metal1","via1","metal2"),
@@ -319,8 +321,10 @@ class sram_1bank(sram_base):
 
         route_map = list(zip(bank_names, dff_names))
         dff_pins = {key: self.data_dff_inst.get_pin(key) for key in dff_names }
-        bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names }   
-        self.create_horizontal_channel_route(route_map, dff_pins, bank_pins, offset)
+        bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names }
+        # Combine the dff and bank pins into a single dictionary of pin name to pin.
+        all_pins = {**dff_pins, **bank_pins}
+        self.create_horizontal_channel_route(route_map, all_pins, offset)
                 
             
 
@@ -332,7 +336,7 @@ class sram_1bank(sram_base):
         """
         
         for n in self.control_logic_outputs:
-            pin = self.control_logic_inst.get_pin(n)
+            pin = self.control_logic_inst[0].get_pin(n)
             self.add_label(text=n,
                            layer=pin.layer,
                            offset=pin.center())

compiler/sram_base.py

@@ -28,6 +28,16 @@ class sram_base(design):
 
     def add_pins(self):
         """ Add pins for entire SRAM. """
+        self.read_index = []
+        port_number = 0
+        for port in range(OPTS.num_rw_ports):
+            self.read_index.append("{}".format(port_number))
+            port_number += 1
+        for port in range(OPTS.num_w_ports):
+            port_number += 1
+        for port in range(OPTS.num_r_ports):
+            self.read_index.append("{}".format(port_number))
+            port_number += 1
     
         for port in range(self.total_write):
             for bit in range(self.word_size):
@@ -41,11 +51,15 @@ class sram_base(design):
         self.control_logic_inputs=self.control_logic.get_inputs()
         self.control_logic_outputs=self.control_logic.get_outputs()
         
-        self.add_pin_list(self.control_logic_inputs,"INPUT")
+        #self.add_pin_list(self.control_logic_inputs,"INPUT")
+        self.add_pin("csb","INPUT")
+        for port in range(self.total_write):
+            self.add_pin("web{}".format(port),"INPUT")
+        self.add_pin("clk","INPUT")
 
         for port in range(self.total_read):
             for bit in range(self.word_size):
-                self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT")
+                self.add_pin("DOUT{0}[{1}]".format(self.read_index[port],bit),"OUTPUT")
         
         self.add_pin("vdd","POWER")
         self.add_pin("gnd","GROUND")
@@ -213,10 +227,6 @@ class sram_base(design):
         c = reload(__import__(OPTS.control_logic))
         self.mod_control_logic = getattr(c, OPTS.control_logic)
 
-        c = reload(__import__(OPTS.ms_flop))
-        self.mod_ms_flop = getattr(c, OPTS.ms_flop)
-        self.ms_flop = self.mod_ms_flop()
-
         
         from control_logic import control_logic
         # Create the control logic module
@@ -234,7 +244,7 @@ class sram_base(design):
         else:
             self.col_addr_dff = None
 
-        self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size*self.total_ports)
+        self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size*self.total_write)
         self.add_mod(self.data_dff)
         
         # Create the bank module (up to four are instantiated)
@@ -262,7 +272,7 @@ class sram_base(design):
         temp = []
         for port in range(self.total_read):
             for bit in range(self.word_size):
-                temp.append("DOUT{0}[{1}]".format(port,bit))
+                temp.append("DOUT{0}[{1}]".format(self.read_index[port],bit))
         for port in range(self.total_write):
             for bit in range(self.word_size):
                 temp.append("BANK_DIN{0}[{1}]".format(port,bit))
@@ -273,7 +283,7 @@ class sram_base(design):
             for port in range(self.total_ports):
                 temp.append("bank_sel{0}[{1}]".format(port,bank_num))
         for port in range(self.total_read):
-            temp.append("s_en{0}".format(port))
+            temp.append("s_en{0}".format(self.read_index[port]))
         for port in range(self.total_write):
             temp.append("w_en{0}".format(port))
         temp.extend(["clk_buf_bar","clk_buf" , "vdd", "gnd"])
@@ -321,10 +331,10 @@ class sram_base(design):
         # inputs, outputs/output/bar
         inputs = []
         outputs = []
-        for k in range(self.total_ports):
+        for port in range(self.total_ports):
             for i in range(self.row_addr_size):
-                inputs.append("ADDR{}[{}]".format(k,i+self.col_addr_size))
-                outputs.append("A{}[{}]".format(k,i+self.col_addr_size))
+                inputs.append("ADDR{}[{}]".format(port,i+self.col_addr_size))
+                outputs.append("A{}[{}]".format(port,i+self.col_addr_size))
 
         self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
         return inst
@@ -337,10 +347,10 @@ class sram_base(design):
         # inputs, outputs/output/bar
         inputs = []
         outputs = []
-        for k in range(self.total_ports):
+        for port in range(self.total_ports):
             for i in range(self.col_addr_size):
-                inputs.append("ADDR{}[{}]".format(k,i))
-                outputs.append("A{}[{}]".format(k,i))
+                inputs.append("ADDR{}[{}]".format(port,i))
+                outputs.append("A{}[{}]".format(port,i))
 
         self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
         return inst
@@ -353,20 +363,24 @@ class sram_base(design):
         # inputs, outputs/output/bar
         inputs = []
         outputs = []
-        for k in range(self.total_write):
+        for port in range(self.total_write):
             for i in range(self.word_size):
-                inputs.append("DIN{}[{}]".format(k,i))
-                outputs.append("BANK_DIN{}[{}]".format(k,i))
+                inputs.append("DIN{}[{}]".format(port,i))
+                outputs.append("BANK_DIN{}[{}]".format(port,i))
 
         self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
         return inst
         
-    def create_control_logic(self):
+    def create_control_logic(self, port):
         """ Add and place control logic """
         inst = self.add_inst(name="control",
                              mod=self.control_logic)
               
-        self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"])
+        self.connect_inst(["csb", "web{}".format(port), "clk",
+                           "s_en{}".format(port), "w_en{}".format(port), "clk_buf_bar", "clk_buf",
+                           "vdd", "gnd"])
+        
+        #self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"])
         return inst
         
         

compiler/tests/04_precharge_test.py

@@ -17,24 +17,25 @@ class precharge_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import precharge
         import tech
-
+        
         debug.info(2, "Checking precharge for handmade bitcell")
         tx = precharge.precharge(name="precharge_driver", size=1)
         self.local_check(tx)
         
-        debug.info(2, "Checking precharge for pbitcell")
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 2
-        OPTS.num_r_ports = 2
-        OPTS.num_w_ports = 2
-        tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0")
-        self.local_check(tx)
-        
-        tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="wbl0", bitcell_br="wbl_bar0")
-        self.local_check(tx)
-        
-        tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="rbl0", bitcell_br="rbl_bar0")
-        self.local_check(tx)
+        if OPTS.multiport_check:
+            debug.info(2, "Checking precharge for pbitcell")
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_r_ports = 1
+            OPTS.num_w_ports = 1
+            tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(tx)
+            
+            tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1")
+            self.local_check(tx)
+            
+            tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2")
+            self.local_check(tx)
 
         globals.end_openram()
         

compiler/tests/04_single_level_column_mux_test.py

@@ -23,6 +23,21 @@ class single_level_column_mux_test(openram_test):
         debug.info(2, "Checking column mux")
         tx = single_level_column_mux.single_level_column_mux(tx_size=8)
         self.local_check(tx)
+        
+        if OPTS.multiport_check:
+            debug.info(2, "Checking column mux for pbitcell")
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_r_ports = 1
+            OPTS.num_w_ports = 1
+            tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(tx)
+            
+            tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl1", bitcell_br="br1")
+            self.local_check(tx)
+            
+            tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
+            self.local_check(tx)
 
         globals.end_openram()
         

compiler/tests/07_single_level_column_mux_array_test.py

@@ -27,6 +27,33 @@ class single_level_column_mux_test(openram_test):
         debug.info(1, "Testing sample for 8-way column_mux_array")
         a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4)
         self.local_check(a)
+        
+        if OPTS.multiport_check:
+            debug.info(2, "Checking column mux array for pbitcell")
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_r_ports = 1
+            OPTS.num_w_ports = 1
+            
+            debug.info(1, "Testing sample for 2-way column_mux_array")
+            a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(a)
+
+            debug.info(1, "Testing sample for 4-way column_mux_array")
+            a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(a)
+
+            debug.info(1, "Testing sample for 8-way column_mux_array")
+            a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(a)
+            
+            debug.info(1, "Testing sample for 8-way column_mux_array")
+            a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl1", bitcell_br="br1")
+            self.local_check(a)
+            
+            debug.info(1, "Testing sample for 8-way column_mux_array")
+            a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
+            self.local_check(a)
 
         globals.end_openram()
         

compiler/tests/08_precharge_array_test.py

@@ -22,20 +22,21 @@ class precharge_test(openram_test):
         pc = precharge_array.precharge_array(columns=3)
         self.local_check(pc)
         
-        debug.info(2, "Checking precharge for pbitcell")
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 2
-        OPTS.num_r_ports = 2
-        OPTS.num_w_ports = 2
-        
-        pc = precharge_array.precharge_array(columns=3, bitcell_bl="rwbl0", bitcell_br="rwbl_bar0")
-        self.local_check(pc)
-        
-        pc = precharge_array.precharge_array(columns=3, bitcell_bl="wbl0", bitcell_br="wbl_bar0")
-        self.local_check(pc)
-        
-        pc = precharge_array.precharge_array(columns=3, bitcell_bl="rbl0", bitcell_br="rbl_bar0")
-        self.local_check(pc)
+        if OPTS.multiport_check:
+            debug.info(2, "Checking precharge array for pbitcell")
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_r_ports = 1
+            OPTS.num_w_ports = 1
+            
+            pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
+            self.local_check(pc)
+            
+            pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl1", bitcell_br="br1")
+            self.local_check(pc)
+            
+            pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
+            self.local_check(pc)
 
         globals.end_openram()
 

compiler/tests/08_wordline_driver_test.py

@@ -20,20 +20,19 @@ class wordline_driver_test(openram_test):
         import wordline_driver
         import tech
 
-        # check wordline driver array in single port
         debug.info(2, "Checking driver")
         tx = wordline_driver.wordline_driver(rows=8)
         self.local_check(tx)
 
-        # check wordline driver array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(2, "Checking driver (multi-port case)")
-        tx = wordline_driver.wordline_driver(rows=8)
-        self.local_check(tx)
+        if OPTS.multiport_check:
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_w_ports = 0
+            OPTS.num_r_ports = 0
+            
+            debug.info(2, "Checking driver (multi-port case)")
+            tx = wordline_driver.wordline_driver(rows=8)
+            self.local_check(tx)
 
         globals.end_openram()
         

compiler/tests/09_sense_amp_array_test.py

@@ -17,7 +17,6 @@ class sense_amp_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import sense_amp_array
 
-        # check sense amp array in single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
         self.local_check(a)
@@ -26,19 +25,19 @@ class sense_amp_test(openram_test):
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
         self.local_check(a)
         
-        # check sense amp array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
-        a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
-        self.local_check(a)
+        if OPTS.multiport_check:
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_w_ports = 0
+            OPTS.num_r_ports = 0
+            
+            debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
+            a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
+            self.local_check(a)
 
-        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
-        a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
-        self.local_check(a)
+            debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
+            a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
+            self.local_check(a)
         
         globals.end_openram()
         

compiler/tests/10_write_driver_array_test.py

@@ -17,7 +17,6 @@ class write_driver_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import write_driver_array
 
-        # check write driver array in single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
         a = write_driver_array.write_driver_array(columns=8, word_size=8)
         self.local_check(a)
@@ -26,19 +25,19 @@ class write_driver_test(openram_test):
         a = write_driver_array.write_driver_array(columns=16, word_size=8)
         self.local_check(a)
         
-        # check write driver array in multi-port
-        OPTS.bitcell = "pbitcell"
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 0
-        OPTS.num_r_ports = 0
-        
-        debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
-        a = write_driver_array.write_driver_array(columns=8, word_size=8)
-        self.local_check(a)
+        if OPTS.multiport_check:
+            OPTS.bitcell = "pbitcell"
+            OPTS.num_rw_ports = 1
+            OPTS.num_w_ports = 0
+            OPTS.num_r_ports = 0
+            
+            debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
+            a = write_driver_array.write_driver_array(columns=8, word_size=8)
+            self.local_check(a)
 
-        debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
-        a = write_driver_array.write_driver_array(columns=16, word_size=8)
-        self.local_check(a)
+            debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
+            a = write_driver_array.write_driver_array(columns=16, word_size=8)
+            self.local_check(a)
         
         globals.end_openram()
 

compiler/tests/11_ms_flop_array_test.py

@@ -1,35 +0,0 @@
-#!/usr/bin/env python3
-"""
-Run a regression test on a dff_array.
-"""
-
-import unittest
-from testutils import header,openram_test
-import sys,os
-sys.path.append(os.path.join(sys.path[0],".."))
-import globals
-from globals import OPTS
-import debug
-
-class dff_array_test(openram_test):
-
-    def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        import ms_flop_array
-
-        debug.info(2, "Testing ms_flop_array for columns=8, word_size=8")
-        a = ms_flop_array.ms_flop_array(columns=8, word_size=8)
-        self.local_check(a)
-
-        debug.info(2, "Testing ms_flop_array for columns=16, word_size=8")
-        a = ms_flop_array.ms_flop_array(columns=16, word_size=8)
-        self.local_check(a)
-        
-        globals.end_openram()
-
-# instantiate a copdsay of the class to actually run the test
-if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
-    del sys.argv[1:]
-    header(__file__, OPTS.tech_name)
-    unittest.main()

compiler/tests/19_psingle_bank_test.py

@@ -33,6 +33,25 @@ class psingle_bank_test(openram_test):
         debug.info(1, "No column mux")
         a = bank(c, name="bank1_1rw_0w_0r_single")
         self.local_check(a)
+        
+        c.num_words=32
+        c.words_per_row=2
+        debug.info(1, "Two way column mux")
+        a = bank(c, name="bank1_1rw_0w_0r_single")
+        self.local_check(a)
+        
+        c.num_words=64
+        c.words_per_row=4
+        debug.info(1, "Four way column mux")
+        a = bank(c, name="bank1_1rw_0w_0r_single")
+        self.local_check(a)
+        
+        c.num_words=128
+        c.words_per_row=8
+        debug.info(1, "Four way column mux")
+        a = bank(c, name="bank1_1rw_0w_0r_single")
+        self.local_check(a)
+        
         """
         # multiport can't generate layout yet on the bank level
         OPTS.netlist_only = True
@@ -120,7 +139,7 @@ class psingle_bank_test(openram_test):
         self.local_check(a)
         """
         
-        globals.end_openram()
+        #globals.end_openram()
         
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":

compiler/tests/20_psram_1bank_test.py

@@ -0,0 +1,73 @@
+#!/usr/bin/env python3
+"""
+Run a regression test on a 1 bank SRAM
+"""
+
+import unittest
+from testutils import header,openram_test
+import sys,os
+sys.path.append(os.path.join(sys.path[0],".."))
+import globals
+from globals import OPTS
+import debug
+
+@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
+class sram_1bank_test(openram_test):
+
+    def runTest(self):        
+        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        from sram import sram
+        from sram_config import sram_config
+        OPTS.bitcell = "pbitcell"
+        
+        # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        c = sram_config(word_size=4,
+                        num_words=16,
+                        num_banks=1)
+        c.words_per_row=1
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        """
+        OPTS.rw_ports = 1
+        OPTS.w_ports = 1
+        OPTS.r_ports = 1
+        OPTS.netlist_only = True
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        c.num_words=32
+        c.words_per_row=2
+        debug.info(1, "Single bank two way column mux with control logic")
+        a = sram(c, "sram2")
+        self.local_check(a, final_verification=True)
+
+        c.num_words=64
+        c.words_per_row=4
+        debug.info(1, "Single bank, four way column mux with control logic")
+        a = sram(c, "sram3")
+        self.local_check(a, final_verification=True)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        debug.info(1, "Single bank, eight way column mux with control logic")
+        a = sram(c, "sram4")
+        self.local_check(a, final_verification=True)
+        """
+        #globals.end_openram()
+        
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main()

compiler/tests/21_hspice_delay_test.py

@@ -50,28 +50,29 @@ class timing_sram_test(openram_test):
         slews = [tech.spice["rise_time"]*2]
         data = d.analyze(probe_address, probe_data, slews, loads)
 
+        #Assumes single rw port (6t sram)
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [2.5829000000000004],
-                            'delay_lh': [0.2255964],
+            golden_data = {'delay_hl0': [2.5829000000000004],
+                            'delay_lh0': [0.2255964],
                             'leakage_power': 0.0019498999999999996,
                             'min_period': 4.844,
-                            'read0_power': [0.055371399999999994],
-                            'read1_power': [0.0520225],
-                            'slew_hl': [0.0794261],
-                            'slew_lh': [0.0236264],
-                            'write0_power': [0.06545659999999999],
-                            'write1_power': [0.057846299999999996]}
-        elif OPTS.tech_name == "scn3me_subm":
-            golden_data = {'delay_hl': [4.0249],
-                            'delay_lh': [2.2611],
-                            'leakage_power': 0.0257389,
+                            'read0_power0': [0.055371399999999994],
+                            'read1_power0': [0.0520225],
+                            'slew_hl0': [0.0794261],
+                            'slew_lh0': [0.0236264],
+                            'write0_power0': [0.06545659999999999],
+                            'write1_power0': [0.057846299999999996]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'delay_hl0': [3.452],
+                            'delay_lh0': [1.3792000000000002],
+                            'leakage_power': 0.0257065,
                             'min_period': 4.688,
-                            'read0_power': [24.9279],
-                            'read1_power': [24.0219],
-                            'slew_hl': [0.8500753999999999],
-                            'slew_lh': [0.4122653],
-                            'write0_power': [28.197600000000005],
-                            'write1_power': [25.685]}
+                            'read0_power0': [15.0755],
+                            'read1_power0': [14.4526],
+                            'slew_hl0': [0.6137363],
+                            'slew_lh0': [0.3381045],
+                            'write0_power0': [16.9203],
+                            'write1_power0': [15.367]}
         else:
             self.assertTrue(False) # other techs fail
         # Check if no too many or too few results

compiler/tests/21_hspice_setuphold_test.py

@@ -35,15 +35,15 @@ class timing_setup_test(openram_test):
         data = sh.analyze(slews,slews)
         #print data
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'setup_times_LH': [0.014648399999999999],
-                           'hold_times_LH': [0.0024414],
-                           'hold_times_HL': [-0.0036620999999999997],
-                           'setup_times_HL': [0.0085449]}
-        elif OPTS.tech_name == "scn3me_subm":
-            golden_data = {'setup_times_LH': [0.08178709999999999],
-                           'hold_times_LH': [0.0024414],
-                           'hold_times_HL': [-0.0646973],
-                           'setup_times_HL': [0.0390625]}
+            golden_data = {'hold_times_HL': [-0.0097656],
+                           'hold_times_LH': [-0.0158691],
+                           'setup_times_HL': [0.026855499999999997],
+                           'setup_times_LH': [0.032959]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'hold_times_HL': [-0.0891113],
+                            'hold_times_LH': [-0.0769043],
+                            'setup_times_HL': [0.1184082],
+                            'setup_times_LH': [0.1733398]}
         else:
             self.assertTrue(False) # other techs fail
 

compiler/tests/21_ngspice_delay_test.py

@@ -51,27 +51,27 @@ class timing_sram_test(openram_test):
         data = d.analyze(probe_address, probe_data, slews, loads)
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [2.584251],
-                            'delay_lh': [0.22870469999999998],
+            golden_data = {'delay_hl0': [2.584251],
+                            'delay_lh0': [0.22870469999999998],
                             'leakage_power': 0.0009567935,
                             'min_period': 4.844,
-                            'read0_power': [0.0547588],
-                            'read1_power': [0.051159970000000006],
-                            'slew_hl': [0.08164099999999999],
-                            'slew_lh': [0.025474979999999998],
-                            'write0_power': [0.06513271999999999],
-                            'write1_power': [0.058057000000000004]}
-        elif OPTS.tech_name == "scn3me_subm":
-            golden_data = {'delay_hl': [4.221382999999999],
-                            'delay_lh': [2.6459520000000003],
-                            'leakage_power': 0.0013865260000000001,
+                            'read0_power0': [0.0547588],
+                            'read1_power0': [0.051159970000000006],
+                            'slew_hl0': [0.08164099999999999],
+                            'slew_lh0': [0.025474979999999998],
+                            'write0_power0': [0.06513271999999999],
+                            'write1_power0': [0.058057000000000004]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'delay_hl0': [3.644147],
+                            'delay_lh0': [1.629815],
+                            'leakage_power': 0.0009299118999999999,
                             'min_period': 4.688,
-                            'read0_power': [26.699669999999998],
-                            'read1_power': [26.13123],
-                            'slew_hl': [0.9821776000000001],
-                            'slew_lh': [1.5791520000000001],
-                            'write0_power': [30.71939],
-                            'write1_power': [27.44753]}
+                            'read0_power0': [16.28732],
+                            'read1_power0': [15.75155],
+                            'slew_hl0': [0.6722473],
+                            'slew_lh0': [0.3386347],
+                            'write0_power0': [18.545450000000002],
+                            'write1_power0': [16.81084]}
         else:
             self.assertTrue(False) # other techs fail
 

compiler/tests/21_ngspice_setuphold_test.py

@@ -35,15 +35,15 @@ class timing_setup_test(openram_test):
         data = sh.analyze(slews,slews)
         #print data
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'setup_times_LH': [0.01464844],
-                           'hold_times_LH': [0.0024414059999999997],
-                           'hold_times_HL': [-0.003662109],
-                           'setup_times_HL': [0.008544922]}
-        elif OPTS.tech_name == "scn3me_subm":
-            golden_data = {'setup_times_LH': [0.07568359],
-                           'hold_times_LH': [0.008544922],
-                           'hold_times_HL': [-0.05859374999999999],
-                           'setup_times_HL': [0.03295898]}
+            golden_data = {'hold_times_HL': [-0.01586914],
+                           'hold_times_LH': [-0.01586914],
+                           'setup_times_HL': [0.02685547],
+                           'setup_times_LH': [0.03295898]}
+        elif OPTS.tech_name == "scn4m_subm":
+            golden_data = {'hold_times_HL': [-0.08911132999999999],
+                            'hold_times_LH': [-0.0769043],
+                            'setup_times_HL': [0.1184082],
+                            'setup_times_LH': [0.1672363]}
         else:
             self.assertTrue(False) # other techs fail
 

compiler/tests/config_20_scn4m_subm.py

@@ -0,0 +1,13 @@
+word_size = 1
+num_words = 16
+num_banks = 1
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
+

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib

@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        direction  : input; 
+        capacitance : 0.2091;  
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
         memory_read(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.027",\
-                   "0.009, 0.015, 0.027",\
-                   "0.009, 0.015, 0.027");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 0.2091;  

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib

@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        direction  : input; 
+        capacitance : 0.2091;  
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
         memory_read(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 0.2091;  

compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib

@@ -87,16 +87,16 @@ cell (sram_2_16_1_freepdk45){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
+        direction  : input; 
+        capacitance : 0.2091;  
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 1.6728;  
         min_capacitance : 0.052275;  
         memory_read(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_freepdk45){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.027",\
-                   "0.009, 0.015, 0.027",\
-                   "0.009, 0.015, 0.027");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 0.2091;  

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib

@@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        direction  : input; 
+        capacitance : 9.8242;  
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 78.5936;  
         min_capacitance : 2.45605;  
         memory_read(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 9.8242;  

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib

@@ -87,20 +87,20 @@ cell (sram_2_16_1_scn3me_subm){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        direction  : input; 
+        capacitance : 9.8242;  
         memory_write(){ 
-            address : ADDR; 
+            address : ADDR0; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 78.5936;  
         min_capacitance : 2.45605;  
         memory_read(){ 
-            address : ADDR; 
+            address : ADDR0; 
         }
         pin(DOUT[1:0]){
         timing(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009",\
-                   "0.009, 0.009, 0.009");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001",\
-                   "0.001, 0.001, 0.001");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 9.8242;  

compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib

@@ -87,16 +87,16 @@ cell (sram_2_16_1_scn3me_subm){
     cell_leakage_power : 0;
     bus(DIN){
         bus_type  : DATA; 
-        direction  : in; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
+        direction  : input; 
+        capacitance : 9.8242;  
         memory_write(){ 
             address : ADDR; 
             clocked_on  : clk; 
         }
+    }
     bus(DOUT){
         bus_type  : DATA; 
-        direction  : out; 
+        direction  : output; 
         max_capacitance : 78.5936;  
         min_capacitance : 2.45605;  
         memory_read(){ 
@@ -229,39 +229,6 @@ cell (sram_2_16_1_scn3me_subm){
         }
     }
 
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027",\
-                   "0.033, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
     pin(WEb){
         direction  : input; 
         capacitance : 9.8242;  

compiler/tests/golden/sram_2_16_1_scn4m_subm.sp

@@ -0,0 +1,681 @@
+* OpenRAM generated memory.
+* User: mrg
+.global vdd gnd
+*master-slave flip-flop with both output and inverted ouput
+
+.subckt ms_flop din dout dout_bar clk vdd gnd
+xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
+xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
+.ends flop
+
+.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
+*clk inverter
+mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
+mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1
+
+*transmission gate 1
+mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1
+mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1
+
+*foward inverter
+mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1
+mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1
+
+*backward inverter
+mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1
+mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1
+
+*transmission gate 2
+mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
+mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
+.ends dlatch
+
+
+.SUBCKT inv_nmos11 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS inv_nmos11
+
+.SUBCKT inv_pmos12 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS inv_pmos12
+
+.SUBCKT pinv A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos11
+Xpinv_pmos Z A vdd vdd inv_pmos12
+.ENDS pinv
+
+.SUBCKT nand_2_nmos13 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos13
+
+.SUBCKT nand_2_nmos24 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos24
+
+.SUBCKT nand_2_pmos15 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos15
+
+.SUBCKT nand_2_pmos26 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos26
+
+.SUBCKT nand2 A B Z vdd gnd
+Xnmos1 Z A net1 gnd nand_2_nmos13
+Xnmos2 net1 B gnd gnd nand_2_nmos24
+Xpmos1 vdd A Z vdd nand_2_pmos15
+Xpmos2 Z B vdd vdd nand_2_pmos26
+.ENDS nand2
+
+.SUBCKT nand_3_nmos17 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos17
+
+.SUBCKT nand_3_nmos28 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos28
+
+.SUBCKT nand_3_nmos39 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos39
+
+.SUBCKT nand_3_pmos110 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos110
+
+.SUBCKT nand_3_pmos211 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos211
+
+.SUBCKT nand_3_pmos312 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos312
+
+.SUBCKT NAND3 A B C Z vdd gnd
+Xnmos1 net2 A gnd gnd nand_3_nmos17
+Xnmos2 net1 B net2 gnd nand_3_nmos28
+Xnmos3 Z C net1 gnd nand_3_nmos39
+Xpmos1 Z A vdd vdd nand_3_pmos110
+Xpmos2 vdd B Z vdd nand_3_pmos211
+Xpmos3 Z C vdd vdd nand_3_pmos312
+.ENDS NAND3
+
+.SUBCKT inv_nmos113 D G S B
+Mnmos D G S B n m=4 w=1.2u l=0.6u
+.ENDS inv_nmos113
+
+.SUBCKT inv_pmos114 D G S B
+Mpmos D G S B p m=4 w=2.4u l=0.6u
+.ENDS inv_pmos114
+
+.SUBCKT pinv4 A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos113
+Xpinv_pmos Z A vdd vdd inv_pmos114
+.ENDS pinv4
+
+.SUBCKT nor_2_nmos123 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos123
+
+.SUBCKT nor_2_nmos224 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos224
+
+.SUBCKT nor_2_pmos125 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos125
+
+.SUBCKT nor_2_pmos226 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos226
+
+.SUBCKT nor2 A B Z vdd gnd
+Xnmos1 Z A gnd gnd nor_2_nmos123
+Xnmos2 Z B gnd gnd nor_2_nmos224
+Xpmos1 vdd A net1 vdd nor_2_pmos125
+Xpmos2 net1 B Z vdd nor_2_pmos226
+.ENDS nor2
+
+.SUBCKT msf_control DATA[0] DATA[1] DATA[2] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] data_in[2] data_in_bar[2] clk vdd gnd
+XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
+XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
+XXdff2 DATA[2] data_in[2] data_in_bar[2] clk vdd gnd ms_flop
+.ENDS msf_control
+
+*********************** "cell_6t" ******************************
+.SUBCKT replica_cell_6t bl br wl vdd gnd
+M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u
+M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u
+M_3 br wl net_2 gnd n W='1.2u' L=0.6u
+M_4 bl wl gnd gnd n W='1.2u' L=0.6u
+M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u
+M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u
+.ENDS	$ replica_cell_6t
+
+*********************** "cell_6t" ******************************
+.SUBCKT cell_6t bl br wl vdd gnd
+M_1 net_1 net_2 vdd vdd p W='0.9u' L=1.2u
+M_2 net_2 net_1 vdd vdd p W='0.9u' L=1.2u
+M_3 br wl net_2 gnd n W='1.2u' L=0.6u
+M_4 bl wl net_1 gnd n W='1.2u' L=0.6u
+M_5 net_2 net_1 gnd gnd n W='2.4u' L=0.6u
+M_6 net_1 net_2 gnd gnd n W='2.4u' L=0.6u
+.ENDS	$ cell_6t
+
+.SUBCKT bitline_load bl[0] br[0] wl[0] wl[1] vdd gnd
+Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
+Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
+.ENDS bitline_load
+
+.SUBCKT inv_nmos127 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS inv_nmos127
+
+.SUBCKT inv_pmos128 D G S B
+Mpmos D G S B p m=1 w=3.6u l=0.6u
+.ENDS inv_pmos128
+
+.SUBCKT delay_chain_inv A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos127
+Xpinv_pmos Z A vdd vdd inv_pmos128
+.ENDS delay_chain_inv
+
+.SUBCKT delay_chain clk_in clk_out vdd gnd
+Xinv_chain0 clk_in s1 vdd gnd delay_chain_inv
+Xinv_chain1 s1 s2 vdd gnd delay_chain_inv
+Xinv_chain2 s2 s3 vdd gnd delay_chain_inv
+Xinv_chain3 s3 clk_out vdd gnd delay_chain_inv
+.ENDS delay_chain
+
+.SUBCKT inv_nmos129 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS inv_nmos129
+
+.SUBCKT inv_pmos130 D G S B
+Mpmos D G S B p m=1 w=3.6u l=0.6u
+.ENDS inv_pmos130
+
+.SUBCKT RBL_inv A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos129
+Xpinv_pmos Z A vdd vdd inv_pmos130
+.ENDS RBL_inv
+
+.SUBCKT nor_2_nmos139 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos139
+
+.SUBCKT nor_2_nmos240 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos240
+
+.SUBCKT nor_2_pmos141 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos141
+
+.SUBCKT nor_2_pmos242 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos242
+
+.SUBCKT replica_bitline_nor2 A B Z vdd gnd
+Xnmos1 Z A gnd gnd nor_2_nmos139
+Xnmos2 Z B gnd gnd nor_2_nmos240
+Xpmos1 vdd A net1 vdd nor_2_pmos141
+Xpmos2 net1 B Z vdd nor_2_pmos242
+.ENDS replica_bitline_nor2
+
+.SUBCKT access_tx43 D G S B
+Mpmos D G S B p m=1 w=1.2u l=0.6u
+.ENDS access_tx43
+
+.SUBCKT replica_bitline en out vdd gnd
+XBL_inv bl[0] out vdd gnd RBL_inv
+XBL_access_tx vdd delayed_en bl[0] vdd access_tx43
+Xdelay_chain en delayed_en vdd gnd delay_chain
+Xbitcell bl[0] br[0] delayed_en vdd gnd replica_cell_6t
+Xload bl[0] br[0] gnd gnd vdd gnd bitline_load
+.ENDS replica_bitline
+
+.SUBCKT control_logic CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd
+Xmsf_control CSb WEb OEb CS_bar CS WE_bar WE OE_bar OE clk vdd gnd msf_control
+Xclk_inverter clk clk_bar vdd gnd pinv4
+Xnor2 clk OE_bar tri_en vdd gnd nor2
+Xnand2_tri_en OE clk_bar tri_en_bar vdd gnd nand2
+Xreplica_bitline rblk pre_s_en vdd gnd replica_bitline
+Xinv_s_en1 pre_s_en_bar s_en vdd gnd pinv
+Xinv_s_en2 pre_s_en pre_s_en_bar vdd gnd pinv
+XNAND3_rblk_bar clk_bar OE CS rblk_bar vdd gnd NAND3
+XNAND3_w_en_bar clk_bar WE CS w_en_bar vdd gnd NAND3
+Xinv_rblk rblk_bar rblk vdd gnd pinv
+Xinv_w_en w_en_bar pre_w_en vdd gnd pinv
+Xinv_w_en1 pre_w_en pre_w_en1 vdd gnd pinv
+Xinv_w_en2 pre_w_en1 w_en vdd gnd pinv
+.ENDS control_logic
+
+.SUBCKT bitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd
+Xbit_r0_c0 bl[0] br[0] wl[0] vdd gnd cell_6t
+Xbit_r1_c0 bl[0] br[0] wl[1] vdd gnd cell_6t
+Xbit_r2_c0 bl[0] br[0] wl[2] vdd gnd cell_6t
+Xbit_r3_c0 bl[0] br[0] wl[3] vdd gnd cell_6t
+Xbit_r4_c0 bl[0] br[0] wl[4] vdd gnd cell_6t
+Xbit_r5_c0 bl[0] br[0] wl[5] vdd gnd cell_6t
+Xbit_r6_c0 bl[0] br[0] wl[6] vdd gnd cell_6t
+Xbit_r7_c0 bl[0] br[0] wl[7] vdd gnd cell_6t
+Xbit_r8_c0 bl[0] br[0] wl[8] vdd gnd cell_6t
+Xbit_r9_c0 bl[0] br[0] wl[9] vdd gnd cell_6t
+Xbit_r10_c0 bl[0] br[0] wl[10] vdd gnd cell_6t
+Xbit_r11_c0 bl[0] br[0] wl[11] vdd gnd cell_6t
+Xbit_r12_c0 bl[0] br[0] wl[12] vdd gnd cell_6t
+Xbit_r13_c0 bl[0] br[0] wl[13] vdd gnd cell_6t
+Xbit_r14_c0 bl[0] br[0] wl[14] vdd gnd cell_6t
+Xbit_r15_c0 bl[0] br[0] wl[15] vdd gnd cell_6t
+Xbit_r0_c1 bl[1] br[1] wl[0] vdd gnd cell_6t
+Xbit_r1_c1 bl[1] br[1] wl[1] vdd gnd cell_6t
+Xbit_r2_c1 bl[1] br[1] wl[2] vdd gnd cell_6t
+Xbit_r3_c1 bl[1] br[1] wl[3] vdd gnd cell_6t
+Xbit_r4_c1 bl[1] br[1] wl[4] vdd gnd cell_6t
+Xbit_r5_c1 bl[1] br[1] wl[5] vdd gnd cell_6t
+Xbit_r6_c1 bl[1] br[1] wl[6] vdd gnd cell_6t
+Xbit_r7_c1 bl[1] br[1] wl[7] vdd gnd cell_6t
+Xbit_r8_c1 bl[1] br[1] wl[8] vdd gnd cell_6t
+Xbit_r9_c1 bl[1] br[1] wl[9] vdd gnd cell_6t
+Xbit_r10_c1 bl[1] br[1] wl[10] vdd gnd cell_6t
+Xbit_r11_c1 bl[1] br[1] wl[11] vdd gnd cell_6t
+Xbit_r12_c1 bl[1] br[1] wl[12] vdd gnd cell_6t
+Xbit_r13_c1 bl[1] br[1] wl[13] vdd gnd cell_6t
+Xbit_r14_c1 bl[1] br[1] wl[14] vdd gnd cell_6t
+Xbit_r15_c1 bl[1] br[1] wl[15] vdd gnd cell_6t
+.ENDS bitcell_array
+
+.SUBCKT lower_pmos44 D G S B
+Mpmos D G S B p m=1 w=1.2u l=0.6u
+.ENDS lower_pmos44
+
+.SUBCKT upper_pmos45 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS upper_pmos45
+
+.SUBCKT precharge_cell bl br clk vdd
+Xlower_pmos bl clk br vdd lower_pmos44
+Xupper_pmos1 bl clk vdd vdd upper_pmos45
+Xupper_pmos2 br clk vdd vdd upper_pmos45
+.ENDS precharge_cell
+
+.SUBCKT precharge_array bl[0] br[0] bl[1] br[1] clk vdd
+Xpre_column_0 bl[0] br[0] clk vdd precharge_cell
+Xpre_column_1 bl[1] br[1] clk vdd precharge_cell
+.ENDS precharge_array
+*********************** "sense_amp" ******************************
+
+.SUBCKT sense_amp bl br dout sclk vdd gnd
+M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u
+M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u
+M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u
+M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u
+M_5 bl sclk dout vdd p W='7.2*1u' L=0.6u
+M_6 br sclk net_1 vdd p W='7.2*1u' L=0.6u
+M_7 net_2 sclk gnd gnd n W='2.7*1u' L=0.6u
+.ENDS	 sense_amp
+
+
+.SUBCKT sense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] sclk vdd gnd
+Xsa_d0 bl[0] br[0] data_out[0] sclk vdd gnd sense_amp
+Xsa_d1 bl[1] br[1] data_out[1] sclk vdd gnd sense_amp
+.ENDS sense_amp_array
+*********************** Write_Driver ******************************
+.SUBCKT write_driver din bl br wen vdd gnd
+
+**** Inverter to conver Data_in to data_in_bar ******
+M_1 net_3 din gnd gnd n W='1.2*1u' L=0.6u
+M_2 net_3 din vdd vdd p W='2.1*1u' L=0.6u
+
+**** 2input nand gate follwed by inverter to drive BL ******
+M_3 net_2 wen net_7 gnd n W='2.1*1u' L=0.6u
+M_4 net_7 din gnd gnd n W='2.1*1u' L=0.6u
+M_5 net_2 wen vdd vdd p W='2.1*1u' L=0.6u
+M_6 net_2 din vdd vdd p W='2.1*1u' L=0.6u
+
+
+M_7 net_1 net_2 vdd vdd p W='2.1*1u' L=0.6u
+M_8 net_1 net_2 gnd gnd n W='1.2*1u' L=0.6u
+
+**** 2input nand gate follwed by inverter to drive BR******
+
+M_9 net_4 wen vdd vdd p W='2.1*1u' L=0.6u
+M_10 net_4 wen net_8 gnd n W='2.1*1u' L=0.6u
+M_11 net_8 net_3 gnd gnd n W='2.1*1u' L=0.6u
+M_12 net_4 net_3 vdd vdd p W='2.1*1u' L=0.6u
+
+M_13 net_6 net_4 vdd vdd p W='2.1*1u' L=0.6u
+M_14 net_6 net_4 gnd gnd n W='1.2*1u' L=0.6u
+
+************************************************
+
+M_15 bl net_6 net_5 gnd n W='3.6*1u' L=0.6u
+M_16 br net_1 net_5 gnd n W='3.6*1u' L=0.6u
+M_17 net_5 wen gnd gnd n W='3.6*1u' L=0.6u
+
+
+
+.ENDS	$ write_driver
+
+
+.SUBCKT write_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] wen vdd gnd
+XXwrite_driver0 data_in[0] bl[0] br[0] wen vdd gnd write_driver
+XXwrite_driver1 data_in[1] bl[1] br[1] wen vdd gnd write_driver
+.ENDS write_driver_array
+
+.SUBCKT inv_nmos147 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS inv_nmos147
+
+.SUBCKT inv_pmos148 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS inv_pmos148
+
+.SUBCKT INVERTER A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos147
+Xpinv_pmos Z A vdd vdd inv_pmos148
+.ENDS INVERTER
+
+.SUBCKT nand_2_nmos149 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos149
+
+.SUBCKT nand_2_nmos250 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos250
+
+.SUBCKT nand_2_pmos151 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos151
+
+.SUBCKT nand_2_pmos252 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos252
+
+.SUBCKT NAND2 A B Z vdd gnd
+Xnmos1 Z A net1 gnd nand_2_nmos149
+Xnmos2 net1 B gnd gnd nand_2_nmos250
+Xpmos1 vdd A Z vdd nand_2_pmos151
+Xpmos2 Z B vdd vdd nand_2_pmos252
+.ENDS NAND2
+
+.SUBCKT nand_2_nmos159 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos159
+
+.SUBCKT nand_2_nmos260 D G S B
+Mnmos D G S B n m=1 w=2.4u l=0.6u
+.ENDS nand_2_nmos260
+
+.SUBCKT nand_2_pmos161 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos161
+
+.SUBCKT nand_2_pmos262 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_2_pmos262
+
+.SUBCKT a_nand_2 A B Z vdd gnd
+Xnmos1 Z A net1 gnd nand_2_nmos159
+Xnmos2 net1 B gnd gnd nand_2_nmos260
+Xpmos1 vdd A Z vdd nand_2_pmos161
+Xpmos2 Z B vdd vdd nand_2_pmos262
+.ENDS a_nand_2
+
+.SUBCKT inv_nmos163 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS inv_nmos163
+
+.SUBCKT inv_pmos164 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS inv_pmos164
+
+.SUBCKT a_inv_1 A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos163
+Xpinv_pmos Z A vdd vdd inv_pmos164
+.ENDS a_inv_1
+
+.SUBCKT pre2x4 A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd
+XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
+XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
+XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
+XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
+XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
+XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
+XXpre2x4_nand[0] A[0] A[1] Z[3] vdd gnd a_nand_2
+XXpre2x4_nand[1] B[0] A[1] Z[2] vdd gnd a_nand_2
+XXpre2x4_nand[2] A[0] B[1] Z[1] vdd gnd a_nand_2
+XXpre2x4_nand[3] B[0] B[1] Z[0] vdd gnd a_nand_2
+.ENDS pre2x4
+
+.SUBCKT nand_3_nmos165 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos165
+
+.SUBCKT nand_3_nmos266 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos266
+
+.SUBCKT nand_3_nmos367 D G S B
+Mnmos D G S B n m=1 w=3.6u l=0.6u
+.ENDS nand_3_nmos367
+
+.SUBCKT nand_3_pmos168 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos168
+
+.SUBCKT nand_3_pmos269 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos269
+
+.SUBCKT nand_3_pmos370 D G S B
+Mpmos D G S B p m=1 w=2.4u l=0.6u
+.ENDS nand_3_pmos370
+
+.SUBCKT a_nand_3 A B C Z vdd gnd
+Xnmos1 net2 A gnd gnd nand_3_nmos165
+Xnmos2 net1 B net2 gnd nand_3_nmos266
+Xnmos3 Z C net1 gnd nand_3_nmos367
+Xpmos1 Z A vdd vdd nand_3_pmos168
+Xpmos2 vdd B Z vdd nand_3_pmos269
+Xpmos3 Z C vdd vdd nand_3_pmos370
+.ENDS a_nand_3
+
+.SUBCKT pre3x8 A[0] A[1] A[2] out[0] out[1] out[2] out[3] out[4] out[5] out[6] out[7] vdd gnd
+XXpre2x4_inv[0] A[0] B[0] vdd gnd a_inv_1
+XXpre2x4_inv[1] A[1] B[1] vdd gnd a_inv_1
+XXpre2x4_inv[2] A[2] B[2] vdd gnd a_inv_1
+XXpre2x4_nand_inv[0] Z[0] out[0] vdd gnd a_inv_1
+XXpre2x4_nand_inv[1] Z[1] out[1] vdd gnd a_inv_1
+XXpre2x4_nand_inv[2] Z[2] out[2] vdd gnd a_inv_1
+XXpre2x4_nand_inv[3] Z[3] out[3] vdd gnd a_inv_1
+XXpre2x4_nand_inv[4] Z[4] out[4] vdd gnd a_inv_1
+XXpre2x4_nand_inv[5] Z[5] out[5] vdd gnd a_inv_1
+XXpre2x4_nand_inv[6] Z[6] out[6] vdd gnd a_inv_1
+XXpre2x4_nand_inv[7] Z[7] out[7] vdd gnd a_inv_1
+XXpre3x8_nand[0] A[0] A[1] A[2] Z[7] vdd gnd a_nand_3
+XXpre3x8_nand[1] A[0] A[1] B[2] Z[6] vdd gnd a_nand_3
+XXpre3x8_nand[2] A[0] B[1] A[2] Z[5] vdd gnd a_nand_3
+XXpre3x8_nand[3] A[0] B[1] B[2] Z[4] vdd gnd a_nand_3
+XXpre3x8_nand[4] B[0] A[1] A[2] Z[3] vdd gnd a_nand_3
+XXpre3x8_nand[5] B[0] A[1] B[2] Z[2] vdd gnd a_nand_3
+XXpre3x8_nand[6] B[0] B[1] A[2] Z[1] vdd gnd a_nand_3
+XXpre3x8_nand[7] B[0] B[1] B[2] Z[0] vdd gnd a_nand_3
+.ENDS pre3x8
+
+.SUBCKT hierarchical_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd
+Xpre[0] A[0] A[1] out[0] out[1] out[2] out[3] vdd gnd pre2x4
+Xpre[1] A[2] A[3] out[4] out[5] out[6] out[7] vdd gnd pre2x4
+XNAND2_[0] out[0] out[4] Z[0] vdd gnd NAND2
+XNAND2_[1] out[0] out[5] Z[1] vdd gnd NAND2
+XNAND2_[2] out[0] out[6] Z[2] vdd gnd NAND2
+XNAND2_[3] out[0] out[7] Z[3] vdd gnd NAND2
+XNAND2_[4] out[1] out[4] Z[4] vdd gnd NAND2
+XNAND2_[5] out[1] out[5] Z[5] vdd gnd NAND2
+XNAND2_[6] out[1] out[6] Z[6] vdd gnd NAND2
+XNAND2_[7] out[1] out[7] Z[7] vdd gnd NAND2
+XNAND2_[8] out[2] out[4] Z[8] vdd gnd NAND2
+XNAND2_[9] out[2] out[5] Z[9] vdd gnd NAND2
+XNAND2_[10] out[2] out[6] Z[10] vdd gnd NAND2
+XNAND2_[11] out[2] out[7] Z[11] vdd gnd NAND2
+XNAND2_[12] out[3] out[4] Z[12] vdd gnd NAND2
+XNAND2_[13] out[3] out[5] Z[13] vdd gnd NAND2
+XNAND2_[14] out[3] out[6] Z[14] vdd gnd NAND2
+XNAND2_[15] out[3] out[7] Z[15] vdd gnd NAND2
+XINVERTER_[0] Z[0] decode_out[0] vdd gnd INVERTER
+XINVERTER_[1] Z[1] decode_out[1] vdd gnd INVERTER
+XINVERTER_[2] Z[2] decode_out[2] vdd gnd INVERTER
+XINVERTER_[3] Z[3] decode_out[3] vdd gnd INVERTER
+XINVERTER_[4] Z[4] decode_out[4] vdd gnd INVERTER
+XINVERTER_[5] Z[5] decode_out[5] vdd gnd INVERTER
+XINVERTER_[6] Z[6] decode_out[6] vdd gnd INVERTER
+XINVERTER_[7] Z[7] decode_out[7] vdd gnd INVERTER
+XINVERTER_[8] Z[8] decode_out[8] vdd gnd INVERTER
+XINVERTER_[9] Z[9] decode_out[9] vdd gnd INVERTER
+XINVERTER_[10] Z[10] decode_out[10] vdd gnd INVERTER
+XINVERTER_[11] Z[11] decode_out[11] vdd gnd INVERTER
+XINVERTER_[12] Z[12] decode_out[12] vdd gnd INVERTER
+XINVERTER_[13] Z[13] decode_out[13] vdd gnd INVERTER
+XINVERTER_[14] Z[14] decode_out[14] vdd gnd INVERTER
+XINVERTER_[15] Z[15] decode_out[15] vdd gnd INVERTER
+.ENDS hierarchical_decoder
+
+.SUBCKT msf_address ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] addr_clk vdd gnd
+XXdff0 ADDR[0] A[0] A_bar[0] addr_clk vdd gnd ms_flop
+XXdff1 ADDR[1] A[1] A_bar[1] addr_clk vdd gnd ms_flop
+XXdff2 ADDR[2] A[2] A_bar[2] addr_clk vdd gnd ms_flop
+XXdff3 ADDR[3] A[3] A_bar[3] addr_clk vdd gnd ms_flop
+.ENDS msf_address
+
+.SUBCKT msf_data_in DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk vdd gnd
+XXdff0 DATA[0] data_in[0] data_in_bar[0] clk vdd gnd ms_flop
+XXdff1 DATA[1] data_in[1] data_in_bar[1] clk vdd gnd ms_flop
+.ENDS msf_data_in
+
+.SUBCKT msf_data_out data_out[0] data_out[1] tri_in[0] tri_in_bar[0] tri_in[1] tri_in_bar[1] sclk vdd gnd
+XXdff0 data_out[0] tri_in[0] tri_in_bar[0] sclk vdd gnd ms_flop
+XXdff1 data_out[1] tri_in[1] tri_in_bar[1] sclk vdd gnd ms_flop
+.ENDS msf_data_out
+*********************** tri_gate ******************************
+
+.SUBCKT tri_gate in out en en_bar vdd gnd
+
+M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u
+M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u
+M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u
+M_4 out en net_2 gnd n W='1.2*1u' L=0.6u
+M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u
+M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u
+
+
+.ENDS	
+
+.SUBCKT tri_gate_array tri_in[0] tri_in[1] DATA[0] DATA[1] en en_bar vdd gnd
+XXtri_gate0 tri_in[0] DATA[0] en en_bar vdd gnd tri_gate
+XXtri_gate1 tri_in[1] DATA[1] en en_bar vdd gnd tri_gate
+.ENDS tri_gate_array
+
+.SUBCKT wordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd
+XWordline_driver_inv_clk0 clk clk_bar[0] vdd gnd INVERTER
+XWordline_driver_nand0 decode_out[0] clk_bar[0] net[0] vdd gnd NAND2
+XWordline_driver_inv0 net[0] wl[0] vdd gnd INVERTER
+XWordline_driver_inv_clk1 clk clk_bar[1] vdd gnd INVERTER
+XWordline_driver_nand1 decode_out[1] clk_bar[1] net[1] vdd gnd NAND2
+XWordline_driver_inv1 net[1] wl[1] vdd gnd INVERTER
+XWordline_driver_inv_clk2 clk clk_bar[2] vdd gnd INVERTER
+XWordline_driver_nand2 decode_out[2] clk_bar[2] net[2] vdd gnd NAND2
+XWordline_driver_inv2 net[2] wl[2] vdd gnd INVERTER
+XWordline_driver_inv_clk3 clk clk_bar[3] vdd gnd INVERTER
+XWordline_driver_nand3 decode_out[3] clk_bar[3] net[3] vdd gnd NAND2
+XWordline_driver_inv3 net[3] wl[3] vdd gnd INVERTER
+XWordline_driver_inv_clk4 clk clk_bar[4] vdd gnd INVERTER
+XWordline_driver_nand4 decode_out[4] clk_bar[4] net[4] vdd gnd NAND2
+XWordline_driver_inv4 net[4] wl[4] vdd gnd INVERTER
+XWordline_driver_inv_clk5 clk clk_bar[5] vdd gnd INVERTER
+XWordline_driver_nand5 decode_out[5] clk_bar[5] net[5] vdd gnd NAND2
+XWordline_driver_inv5 net[5] wl[5] vdd gnd INVERTER
+XWordline_driver_inv_clk6 clk clk_bar[6] vdd gnd INVERTER
+XWordline_driver_nand6 decode_out[6] clk_bar[6] net[6] vdd gnd NAND2
+XWordline_driver_inv6 net[6] wl[6] vdd gnd INVERTER
+XWordline_driver_inv_clk7 clk clk_bar[7] vdd gnd INVERTER
+XWordline_driver_nand7 decode_out[7] clk_bar[7] net[7] vdd gnd NAND2
+XWordline_driver_inv7 net[7] wl[7] vdd gnd INVERTER
+XWordline_driver_inv_clk8 clk clk_bar[8] vdd gnd INVERTER
+XWordline_driver_nand8 decode_out[8] clk_bar[8] net[8] vdd gnd NAND2
+XWordline_driver_inv8 net[8] wl[8] vdd gnd INVERTER
+XWordline_driver_inv_clk9 clk clk_bar[9] vdd gnd INVERTER
+XWordline_driver_nand9 decode_out[9] clk_bar[9] net[9] vdd gnd NAND2
+XWordline_driver_inv9 net[9] wl[9] vdd gnd INVERTER
+XWordline_driver_inv_clk10 clk clk_bar[10] vdd gnd INVERTER
+XWordline_driver_nand10 decode_out[10] clk_bar[10] net[10] vdd gnd NAND2
+XWordline_driver_inv10 net[10] wl[10] vdd gnd INVERTER
+XWordline_driver_inv_clk11 clk clk_bar[11] vdd gnd INVERTER
+XWordline_driver_nand11 decode_out[11] clk_bar[11] net[11] vdd gnd NAND2
+XWordline_driver_inv11 net[11] wl[11] vdd gnd INVERTER
+XWordline_driver_inv_clk12 clk clk_bar[12] vdd gnd INVERTER
+XWordline_driver_nand12 decode_out[12] clk_bar[12] net[12] vdd gnd NAND2
+XWordline_driver_inv12 net[12] wl[12] vdd gnd INVERTER
+XWordline_driver_inv_clk13 clk clk_bar[13] vdd gnd INVERTER
+XWordline_driver_nand13 decode_out[13] clk_bar[13] net[13] vdd gnd NAND2
+XWordline_driver_inv13 net[13] wl[13] vdd gnd INVERTER
+XWordline_driver_inv_clk14 clk clk_bar[14] vdd gnd INVERTER
+XWordline_driver_nand14 decode_out[14] clk_bar[14] net[14] vdd gnd NAND2
+XWordline_driver_inv14 net[14] wl[14] vdd gnd INVERTER
+XWordline_driver_inv_clk15 clk clk_bar[15] vdd gnd INVERTER
+XWordline_driver_nand15 decode_out[15] clk_bar[15] net[15] vdd gnd NAND2
+XWordline_driver_inv15 net[15] wl[15] vdd gnd INVERTER
+.ENDS wordline_driver
+
+.SUBCKT inv_nmos181 D G S B
+Mnmos D G S B n m=4 w=1.2u l=0.6u
+.ENDS inv_nmos181
+
+.SUBCKT inv_pmos182 D G S B
+Mpmos D G S B p m=4 w=2.4u l=0.6u
+.ENDS inv_pmos182
+
+.SUBCKT pinv4x A Z vdd gnd
+Xpinv_nmos Z A gnd gnd inv_nmos181
+Xpinv_pmos Z A vdd vdd inv_pmos182
+.ENDS pinv4x
+
+.SUBCKT nor_2_nmos195 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos195
+
+.SUBCKT nor_2_nmos296 D G S B
+Mnmos D G S B n m=1 w=1.2u l=0.6u
+.ENDS nor_2_nmos296
+
+.SUBCKT nor_2_pmos197 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos197
+
+.SUBCKT nor_2_pmos298 D G S B
+Mpmos D G S B p m=4 w=1.2u l=0.6u
+.ENDS nor_2_pmos298
+
+.SUBCKT NOR2 A B Z vdd gnd
+Xnmos1 Z A gnd gnd nor_2_nmos195
+Xnmos2 Z B gnd gnd nor_2_nmos296
+Xpmos1 vdd A net1 vdd nor_2_pmos197
+Xpmos2 net1 B Z vdd nor_2_pmos298
+.ENDS NOR2
+
+.SUBCKT test_bank1 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd
+Xbitcell_array bl[0] br[0] bl[1] br[1] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] vdd gnd bitcell_array
+Xprecharge_array bl[0] br[0] bl[1] br[1] clk_bar vdd precharge_array
+Xsense_amp_array bl[0] br[0] bl[1] br[1] data_out[0] data_out[1] s_en vdd gnd sense_amp_array
+Xwrite_driver_array data_in[0] data_in[1] bl[0] br[0] bl[1] br[1] w_en vdd gnd write_driver_array
+Xdata_in_flop_array DATA[0] DATA[1] data_in[0] data_in_bar[0] data_in[1] data_in_bar[1] clk_bar vdd gnd msf_data_in
+Xtrigate_data_array data_out[0] data_out[1] DATA[0] DATA[1] tri_en tri_en_bar vdd gnd tri_gate_array
+Xaddress_decoder A[0] A[1] A[2] A[3] decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] vdd gnd hierarchical_decoder
+Xwordline_driver decode_out[0] decode_out[1] decode_out[2] decode_out[3] decode_out[4] decode_out[5] decode_out[6] decode_out[7] decode_out[8] decode_out[9] decode_out[10] decode_out[11] decode_out[12] decode_out[13] decode_out[14] decode_out[15] wl[0] wl[1] wl[2] wl[3] wl[4] wl[5] wl[6] wl[7] wl[8] wl[9] wl[10] wl[11] wl[12] wl[13] wl[14] wl[15] clk vdd gnd wordline_driver
+Xaddress_flop_array ADDR[0] ADDR[1] ADDR[2] ADDR[3] A[0] A_bar[0] A[1] A_bar[1] A[2] A_bar[2] A[3] A_bar[3] clk vdd gnd msf_address
+.ENDS test_bank1
+
+.SUBCKT testsram DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] CSb WEb OEb clk vdd gnd
+Xbank0 DATA[0] DATA[1] ADDR[0] ADDR[1] ADDR[2] ADDR[3] s_en w_en tri_en_bar tri_en clk_bar clk vdd gnd test_bank1
+Xcontrol CSb WEb OEb s_en w_en tri_en tri_en_bar clk_bar clk vdd gnd control_logic
+.ENDS testsram

compiler/tests/golden/sram_2_16_1_scn4m_subm.v

@@ -0,0 +1,47 @@
+// OpenRAM SRAM model
+// Words: 16
+// Word size: 2
+
+module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
+
+  parameter DATA_WIDTH = 2 ;
+  parameter ADDR_WIDTH = 4 ;
+  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
+  parameter DELAY = 3 ;
+
+  inout [DATA_WIDTH-1:0] DATA;
+  input [ADDR_WIDTH-1:0] ADDR;
+  input CSb;             // active low chip select
+  input WEb;             // active low write control
+  input OEb;             // active output enable
+  input clk;             // clock
+
+  reg [DATA_WIDTH-1:0] data_out ;
+  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
+
+  // Tri-State Buffer control
+  // output : When WEb = 1, oeb = 0, csb = 0
+  assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
+
+  // Memory Write Block
+  // Write Operation : When WEb = 0, CSb = 0
+  always @ (posedge clk)
+  begin : MEM_WRITE
+  if ( !CSb && !WEb ) begin
+    mem[ADDR] = DATA;
+    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
+    end
+  end
+
+
+  // Memory Read Block
+  // Read Operation : When WEb = 1, CSb = 0
+  always @ (posedge clk)
+  begin : MEM_READ
+  if (!CSb && WEb) begin
+    data_out <= #(DELAY) mem[ADDR];
+    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
+    end
+  end
+
+endmodule

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib

@@ -0,0 +1,318 @@
+library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1v" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1 ,fF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("2.45605, 9.8242, 78.5936");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (DATA){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (ADDR){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_1_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 60176.520000000004;
+
+    leakage_power () {
+      when : "CSb0";
+      value : 0.000175;
+    }
+    cell_leakage_power : 0;
+    bus(DIN0){
+        bus_type  : DATA; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        memory_write(){ 
+            address : ADDR0; 
+            clocked_on  : clk; 
+        }
+    }
+    bus(DOUT0){
+        bus_type  : DATA; 
+        direction  : output; 
+        max_capacitance : 78.5936;  
+        min_capacitance : 2.45605;  
+        memory_read(){ 
+            address : ADDR0; 
+        }
+        pin(DOUT0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk"; 
+            timing_type : rising_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004");
+            }
+        }
+        }
+    }
+
+    bus(ADDR0){
+        bus_type  : ADDR; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        max_transition       : 0.4;
+        pin(ADDR0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(CSb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(WEb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk){
+        clock             : true;
+        direction  : input; 
+        capacitance : 9.8242;  
+        internal_power(){
+            when : "!CSb0 & clk & !WEb0"; 
+            rise_power(scalar){
+                values("11.3007276371");
+            }
+            fall_power(scalar){
+                values("11.3007276371");
+            }
+        }
+        internal_power(){
+            when : "!CSb0 & !clk & WEb0"; 
+            rise_power(scalar){
+                values("11.3007276371");
+            }
+            fall_power(scalar){
+                values("11.3007276371");
+            }
+        }
+        internal_power(){
+            when : "CSb0"; 
+            rise_power(scalar){
+                values("0");
+            }
+            fall_power(scalar){
+                values("0");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("0.0"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("0"); 
+            }
+            fall_constraint(scalar) {
+                values("0"); 
+            }
+         }
+    }
+    }
+}

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib

@@ -0,0 +1,318 @@
+library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1v" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1 ,fF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("2.45605, 9.8242, 78.5936");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (DATA){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (ADDR){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_1_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 60176.520000000004;
+
+    leakage_power () {
+      when : "CSb0";
+      value : 0.000175;
+    }
+    cell_leakage_power : 0;
+    bus(DIN0){
+        bus_type  : DATA; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        memory_write(){ 
+            address : ADDR0; 
+            clocked_on  : clk; 
+        }
+    }
+    bus(DOUT0){
+        bus_type  : DATA; 
+        direction  : output; 
+        max_capacitance : 78.5936;  
+        min_capacitance : 2.45605;  
+        memory_read(){ 
+            address : ADDR0; 
+        }
+        pin(DOUT0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk"; 
+            timing_type : rising_edge; 
+            cell_rise(CELL_TABLE) {
+            values("0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268");
+            }
+            cell_fall(CELL_TABLE) {
+            values("0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268",\
+                   "0.268, 0.268, 0.268");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004",\
+                   "0.004, 0.004, 0.004");
+            }
+        }
+        }
+    }
+
+    bus(ADDR0){
+        bus_type  : ADDR; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        max_transition       : 0.4;
+        pin(ADDR0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+        }
+    }
+
+    pin(CSb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(WEb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009",\
+                   "0.009, 0.009, 0.009");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001",\
+                   "0.001, 0.001, 0.001");
+            }
+        }
+    }
+
+    pin(clk){
+        clock             : true;
+        direction  : input; 
+        capacitance : 9.8242;  
+        internal_power(){
+            when : "!CSb0 & clk & !WEb0"; 
+            rise_power(scalar){
+                values("11.3007276371");
+            }
+            fall_power(scalar){
+                values("11.3007276371");
+            }
+        }
+        internal_power(){
+            when : "!CSb0 & !clk & WEb0"; 
+            rise_power(scalar){
+                values("11.3007276371");
+            }
+            fall_power(scalar){
+                values("11.3007276371");
+            }
+        }
+        internal_power(){
+            when : "CSb0"; 
+            rise_power(scalar){
+                values("0");
+            }
+            fall_power(scalar){
+                values("0");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("0.0"); 
+            }
+            fall_constraint(scalar) {
+                values("0.0"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("0"); 
+            }
+            fall_constraint(scalar) {
+                values("0"); 
+            }
+         }
+    }
+    }
+}

compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib

@@ -0,0 +1,318 @@
+library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
+    delay_model : "table_lookup";
+    time_unit : "1ns" ;
+    voltage_unit : "1v" ;
+    current_unit : "1mA" ;
+    resistance_unit : "1kohm" ;
+    capacitive_load_unit(1 ,fF) ;
+    leakage_power_unit : "1mW" ;
+    pulling_resistance_unit :"1kohm" ;
+    operating_conditions(OC){
+    process : 1.0 ;
+    voltage : 5.0 ;
+    temperature : 25;
+    }
+
+    input_threshold_pct_fall       :  50.0 ;
+    output_threshold_pct_fall      :  50.0 ;
+    input_threshold_pct_rise       :  50.0 ;
+    output_threshold_pct_rise      :  50.0 ;
+    slew_lower_threshold_pct_fall  :  10.0 ;
+    slew_upper_threshold_pct_fall  :  90.0 ;
+    slew_lower_threshold_pct_rise  :  10.0 ;
+    slew_upper_threshold_pct_rise  :  90.0 ;
+
+    nom_voltage : 5.0;
+    nom_temperature : 25;
+    nom_process : 1.0;
+    default_cell_leakage_power    : 0.0 ;
+    default_leakage_power_density : 0.0 ;
+    default_input_pin_cap    : 1.0 ;
+    default_inout_pin_cap    : 1.0 ;
+    default_output_pin_cap   : 0.0 ;
+    default_max_transition   : 0.5 ;
+    default_fanout_load      : 1.0 ;
+    default_max_fanout   : 4.0 ;
+    default_connection_class : universal ;
+
+    lu_table_template(CELL_TABLE){
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("2.45605, 9.8242, 78.5936");
+    }
+
+    lu_table_template(CONSTRAINT_TABLE){
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+        index_1("0.0125, 0.05, 0.4");
+        index_2("0.0125, 0.05, 0.4");
+    }
+
+    default_operating_conditions : OC; 
+
+
+    type (DATA){
+    base_type : array;
+    data_type : bit;
+    bit_width : 2;
+    bit_from : 0;
+    bit_to : 1;
+    }
+
+    type (ADDR){
+    base_type : array;
+    data_type : bit;
+    bit_width : 4;
+    bit_from : 0;
+    bit_to : 3;
+    }
+
+cell (sram_2_16_1_scn4m_subm){
+    memory(){ 
+    type : ram;
+    address_width : 4;
+    word_width : 2;
+    }
+    interface_timing : true;
+    dont_use  : true;
+    map_only   : true;
+    dont_touch : true;
+    area : 60176.520000000004;
+
+    leakage_power () {
+      when : "CSb0";
+      value : 0.025716199999999998;
+    }
+    cell_leakage_power : 0;
+    bus(DIN0){
+        bus_type  : DATA; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        memory_write(){ 
+            address : ADDR0; 
+            clocked_on  : clk; 
+        }
+    }
+    bus(DOUT0){
+        bus_type  : DATA; 
+        direction  : output; 
+        max_capacitance : 78.5936;  
+        min_capacitance : 2.45605;  
+        memory_read(){ 
+            address : ADDR0; 
+        }
+        pin(DOUT0[1:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095");
+            }
+        }
+        timing(){ 
+            timing_sense : non_unate; 
+            related_pin : "clk"; 
+            timing_type : rising_edge; 
+            cell_rise(CELL_TABLE) {
+            values("1.277, 1.297, 1.475",\
+                   "1.28, 1.3, 1.479",\
+                   "1.347, 1.367, 1.545");
+            }
+            cell_fall(CELL_TABLE) {
+            values("3.217, 3.281, 3.71",\
+                   "3.22, 3.285, 3.714",\
+                   "3.261, 3.325, 3.75");
+            }
+            rise_transition(CELL_TABLE) {
+            values("0.122, 0.164, 0.579",\
+                   "0.122, 0.164, 0.578",\
+                   "0.122, 0.164, 0.58");
+            }
+            fall_transition(CELL_TABLE) {
+            values("0.363, 0.396, 0.958",\
+                   "0.363, 0.396, 0.957",\
+                   "0.366, 0.399, 0.951");
+            }
+        }
+        }
+    }
+
+    bus(ADDR0){
+        bus_type  : ADDR; 
+        direction  : input; 
+        capacitance : 9.8242;  
+        max_transition       : 0.4;
+        pin(ADDR0[3:0]){
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095");
+            }
+        }
+        }
+    }
+
+    pin(CSb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095");
+            }
+        }
+    }
+
+    pin(WEb0){
+        direction  : input; 
+        capacitance : 9.8242;  
+        timing(){ 
+            timing_type : setup_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228",\
+                   "0.179, 0.173, 0.228");
+            }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143",\
+                   "0.125, 0.125, 0.143");
+            }
+        }
+        timing(){ 
+            timing_type : hold_rising; 
+            related_pin  : "clk"; 
+            rise_constraint(CONSTRAINT_TABLE) {
+            values("-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114",\
+                   "-0.065, -0.071, -0.114");
+              }
+            fall_constraint(CONSTRAINT_TABLE) {
+            values("-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095",\
+                   "-0.089, -0.089, -0.095");
+            }
+        }
+    }
+
+    pin(clk){
+        clock             : true;
+        direction  : input; 
+        capacitance : 9.8242;  
+        internal_power(){
+            when : "!CSb0 & clk & !WEb0"; 
+            rise_power(scalar){
+                values("9.141838916666668");
+            }
+            fall_power(scalar){
+                values("9.141838916666668");
+            }
+        }
+        internal_power(){
+            when : "!CSb0 & !clk & WEb0"; 
+            rise_power(scalar){
+                values("8.304491694444444");
+            }
+            fall_power(scalar){
+                values("8.304491694444444");
+            }
+        }
+        internal_power(){
+            when : "CSb0"; 
+            rise_power(scalar){
+                values("0");
+            }
+            fall_power(scalar){
+                values("0");
+            }
+        }
+        timing(){ 
+            timing_type :"min_pulse_width"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("2.344"); 
+            }
+            fall_constraint(scalar) {
+                values("2.344"); 
+            }
+         }
+        timing(){ 
+            timing_type :"minimum_period"; 
+            related_pin  : clk; 
+            rise_constraint(scalar) {
+                values("4.688"); 
+            }
+            fall_constraint(scalar) {
+                values("4.688"); 
+            }
+         }
+    }
+    }
+}

compiler/tests/testutils.py

@@ -183,6 +183,9 @@ class openram_test(unittest.TestCase):
             
             # 4. Check if remaining string matches
             if line1 != line2:
+                #Uncomment if you want to see all the individual chars of the two lines 
+                #print(str([i for i in line1]))
+                #print(str([i for i in line2]))
                 if mismatches==0:
                     debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
                 mismatches += 1
@@ -222,17 +225,21 @@ class openram_test(unittest.TestCase):
         check = filecmp.cmp(filename1,filename2)
         if not check:
             debug.error("MISMATCH file1={0} file2={1}".format(filename1,filename2))
-            f1 = open(filename1,"r")
-            s1 = f1.readlines().decode('utf-8')
+            f1 = open(filename1,mode="r",encoding='utf-8')
+            s1 = f1.readlines()
             f1.close()
-            f2 = open(filename2,"r").decode('utf-8')
+            f2 = open(filename2,mode="r",encoding='utf-8')
             s2 = f2.readlines()
             f2.close()
             mismatches=0
-            for line in difflib.unified_diff(s1, s2):
+            for line in list(difflib.unified_diff(s1, s2)):
                 mismatches += 1
-                self.error("DIFF LINES:",line)
-                if mismatches>10:
+                if mismatches==0:
+                    print("DIFF LINES:")
+
+                if mismatches<11:
+                    print(line.rstrip('\n'))
+                else:
                     return False
             return False
         else:

compiler/verify/__init__.py

@@ -30,7 +30,7 @@ if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45":
     debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.")
     
 if OPTS.drc_exe == None:
-    pass
+    from .none import run_drc,print_drc_stats
 elif "calibre"==OPTS.drc_exe[0]:
     from .calibre import run_drc,print_drc_stats
 elif "assura"==OPTS.drc_exe[0]:
@@ -41,7 +41,7 @@ else:
     debug.warning("Did not find a supported DRC tool.")
 
 if OPTS.lvs_exe == None:
-    pass
+    from .none import run_lvs,print_lvs_stats
 elif "calibre"==OPTS.lvs_exe[0]:
     from .calibre import run_lvs,print_lvs_stats
 elif "assura"==OPTS.lvs_exe[0]:
@@ -53,7 +53,7 @@ else:
 
 
 if OPTS.pex_exe == None:
-    pass
+    from .none import run_pex,print_pex_stats
 elif "calibre"==OPTS.pex_exe[0]:
     from .calibre import run_pex,print_pex_stats
 elif "magic"==OPTS.pex_exe[0]:

compiler/verify/magic.py

@@ -99,7 +99,10 @@ def write_netgen_script(cell_name, sp_name):
     f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name))
     # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
     # Is there a more elegant way to add this when needed?
-    f.write("flatten class {{{0}.spice precharge_array}}\n".format(cell_name))
+    f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name))
+    f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name))
+    f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name))
+    f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name))
     f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
     f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name))
     f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name))

compiler/verify/none.py

@@ -0,0 +1,41 @@
+"""
+This is a DRC/LVS/PEX interface file the case with no DRC/LVS tools.
+
+"""
+import debug
+
+# Only print the warning once.
+drc_warned = False
+lvs_warned = False
+pex_warned = False
+
+def run_drc(cell_name, gds_name, extract=False):
+    global drc_warned
+    if not drc_warned:
+        debug.warning("DRC unable to run.")
+        drc_warned=True
+    # Since we warned, return a failing test.        
+    return 1
+    
+def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
+    global lvs_warned
+    if not lvs_warned:
+        debug.warning("LVS unable to run.")
+        lvs_warned=True
+    # Since we warned, return a failing test.
+    return 1
+
+def run_pex(name, gds_name, sp_name, output=None):
+    global pex_warned    
+    if not pex_warned:
+        debug.warning("PEX unable to run.")
+        pex_warned=True
+    # Since we warned, return a failing test.        
+    return 1
+
+def print_drc_stats():
+    pass
+def print_lvs_stats():
+    pass
+def print_pex_stats():
+    pass

lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log

@@ -84,50 +84,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625)
 [characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 16788.8 seconds
 GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds
 ** GDS: 9.0 seconds

lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log

@@ -85,50 +85,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875)
 [characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 35039.9 seconds
 GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds
 ** GDS: 5.3 seconds

lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log

@@ -83,50 +83,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
 [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 8034.5 seconds
 GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds
 ** GDS: 3.3 seconds

lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log

@@ -83,50 +83,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875)
 [characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 12972.2 seconds
 GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds
 ** GDS: 5.6 seconds

lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log

@@ -83,50 +83,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
 [characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 4457.6 seconds
 GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds
 ** GDS: 1.4 seconds

lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log

@@ -83,50 +83,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
 [characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 5101.6 seconds
 GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds
 ** GDS: 1.8 seconds

lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log

@@ -82,50 +82,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375)
 [characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 9948.6 seconds
 GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds
 ** GDS: 5.9 seconds

lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log

@@ -84,50 +84,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625)
 [characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.0036621094
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
 [characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.015869141
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
 ** Characterization: 3369.3 seconds
 GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds
 ** GDS: 0.8 seconds

lib/scn3me_subm/sram_1rw_128b_1024w_1bank_scn3me_subm.log

@@ -86,50 +86,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 57.5ns (ub: 60.0 lb: 55.0)
 [characterizer.delay/analyze]: Min Period: 60.0n with a delay of 31.821678 / 3.9657764
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 13865.7 seconds
 GDS: Writing to ./sram_1rw_128b_1024w_1bank_scn3me_subm.gds
 ** GDS: 9.5 seconds

lib/scn3me_subm/sram_1rw_128b_1024w_2bank_scn3me_subm.log

@@ -86,50 +86,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25)
 [characterizer.delay/analyze]: Min Period: 17.5n with a delay of 9.657173 / 2.0055267
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 19670.7 seconds
 GDS: Writing to ./sram_1rw_128b_1024w_2bank_scn3me_subm.gds
 ** GDS: 7.8 seconds

lib/scn3me_subm/sram_1rw_128b_1024w_4bank_scn3me_subm.log

@@ -86,50 +86,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 18.125ns (ub: 18.75 lb: 17.5)
 [characterizer.delay/analyze]: Min Period: 18.75n with a delay of 10.525582 / 2.331161
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 24789.5 seconds
 GDS: Writing to ./sram_1rw_128b_1024w_4bank_scn3me_subm.gds
 ** GDS: 4.3 seconds

lib/scn3me_subm/sram_1rw_32b_2048w_1bank_scn3me_subm.log

@@ -84,50 +84,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 16.875ns (ub: 17.5 lb: 16.25)
 [characterizer.delay/analyze]: Min Period: 16.875n with a delay of 9.1997828 / 3.104732
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 10830.5 seconds
 GDS: Writing to ./sram_1rw_32b_2048w_1bank_scn3me_subm.gds
 ** GDS: 5.3 seconds

lib/scn3me_subm/sram_1rw_32b_256w_1bank_scn3me_subm.log

@@ -84,50 +84,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75)
 [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 10.777462 / 1.9428786
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 3663.3 seconds
 GDS: Writing to ./sram_1rw_32b_256w_1bank_scn3me_subm.gds
 ** GDS: 1.2 seconds

lib/scn3me_subm/sram_1rw_32b_512w_1bank_scn3me_subm.log

@@ -84,50 +84,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 19.375ns (ub: 20.0 lb: 18.75)
 [characterizer.delay/analyze]: Min Period: 20.0n with a delay of 11.057892 / 2.1338514
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 4702.5 seconds
 GDS: Writing to ./sram_1rw_32b_512w_1bank_scn3me_subm.gds
 ** GDS: 2.1 seconds

lib/scn3me_subm/sram_1rw_64b_1024w_1bank_scn3me_subm.log

@@ -85,50 +85,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 33.75ns (ub: 35.0 lb: 32.5)
 [characterizer.delay/analyze]: Min Period: 33.75n with a delay of 18.100242 / 3.0216206
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 9134.8 seconds
 GDS: Writing to ./sram_1rw_64b_1024w_1bank_scn3me_subm.gds
 ** GDS: 5.1 seconds

lib/scn3me_subm/sram_1rw_8b_256w_1bank_scn3me_subm.log

@@ -83,50 +83,50 @@ Trimming netlist to speed up characterization.
 [characterizer.delay/find_min_period]: MinPeriod Search: 9.0625ns (ub: 9.375 lb: 8.75)
 [characterizer.delay/analyze]: Min Period: 9.0625n with a delay of 5.0024145 / 1.5312283
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.0125 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.05 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.0125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.052490234
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.052490234
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.05
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.075683594
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.0390625
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.05859375
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.075683594
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0390625
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.05859375
 [characterizer.setup_hold/analyze]: Clock slew: 0.4 Data slew: 0.4
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transistion: 0.14892578
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transistion: 0.026855469
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transistion: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transistion: -0.13183594
+[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.14892578
+[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.026855469
+[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0085449219
+[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.13183594
 ** Characterization: 2269.5 seconds
 GDS: Writing to ./sram_1rw_8b_256w_1bank_scn3me_subm.gds
 ** GDS: 0.6 seconds

technology/freepdk45/sp_lib/ms_flop.sp

@@ -1,29 +0,0 @@
-*master-slave flip-flop with both output and inverted ouput
-
-.SUBCKT dlatch din dout dout_bar clk clk_bar vdd gnd
-*clk inverter
-mPff1 clk_bar clk vdd vdd PMOS_VTG W=180.0n L=50n m=1
-mNff1 clk_bar clk gnd gnd NMOS_VTG W=90n L=50n m=1
-
-*transmission gate 1
-mtmP1 din clk int1 vdd PMOS_VTG W=180.0n L=50n m=1
-mtmN1 din clk_bar int1 gnd NMOS_VTG W=90n L=50n m=1
-
-*foward inverter
-mPff3 dout_bar int1 vdd vdd PMOS_VTG W=180.0n L=50n m=1
-mNff3 dout_bar int1 gnd gnd NMOS_VTG W=90n L=50n m=1
-
-*backward inverter
-mPff4 dout dout_bar vdd vdd PMOS_VTG W=180.0n L=50n m=1
-mNf4 dout dout_bar gnd gnd NMOS_VTG W=90n L=50n m=1
-
-*transmission gate 2
-mtmP2 int1 clk_bar dout vdd PMOS_VTG W=180.0n L=50n m=1
-mtmN2 int1 clk dout gnd NMOS_VTG W=90n L=50n m=1
-.ENDS dlatch
-
-.SUBCKT ms_flop din dout dout_bar clk vdd gnd 
-xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
-xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
-.ENDS flop
-

technology/freepdk45/tech/tech.py

@@ -298,11 +298,11 @@ spice["msflop_leakage"] = 1      # Leakage power of flop in nW
 spice["flop_para_cap"] = 2       # Parasitic Output capacitance in fF
 
 spice["default_event_rate"] = 100           # Default event activity of every gate. MHz
-spice["flop_transisition_prob"] = .5        # Transition probability of inverter.
-spice["inv_transisition_prob"] = .5         # Transition probability of inverter.
-spice["nand2_transisition_prob"] = .1875    # Transition probability of 2-input nand.
-spice["nand3_transisition_prob"] = .1094    # Transition probability of 3-input nand.
-spice["nor2_transisition_prob"] = .1875     # Transition probability of 2-input nor.
+spice["flop_transition_prob"] = .5        # Transition probability of inverter.
+spice["inv_transition_prob"] = .5         # Transition probability of inverter.
+spice["nand2_transition_prob"] = .1875    # Transition probability of 2-input nand.
+spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input nand.
+spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 ###################################################
 ##END Spice Simulation Parameters

technology/scn3me_subm/mag_lib/.magicrc

@@ -1,2 +1,5 @@
 path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech
-tech load SCN3ME_SUBM.30
+tech load SCN3ME_SUBM.30 -noprompt
+scalegrid 1 4
+set GND gnd
+set VDD vdd

technology/scn3me_subm/mag_lib/convertall.sh

@@ -0,0 +1,14 @@
+magic -dnull -noconsole << EOF
+load dff
+gds write dff.gds
+load cell_6t
+gds write cell_6t.gds
+load replica_cell_6t
+gds write replica_cell_6t.gds
+load sense_amp
+gds write sense_amp.gds
+load tri_gate
+gds write tri_gate.gds
+load write_driver
+gds write write_driver.gds
+EOF

technology/scn3me_subm/sp_lib/dff.sp

@@ -1,47 +1,27 @@
+*********************** "dff" ******************************
 * Positive edge-triggered FF
-.subckt dff D Q clk vdd gnd
+.SUBCKT dff D Q clk vdd gnd
 M0 vdd clk a_2_6# vdd p w=12u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M1 a_17_74# D vdd vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M9 vdd Q a_76_84# vdd p w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M10 gnd clk a_2_6# gnd n w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M11 Q a_66_6# vdd vdd p w=12u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M12 a_17_6# D gnd gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M20 gnd Q a_76_6# gnd n w=3u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
 M21 Q a_66_6# gnd gnd n w=6u l=0.6u
-+ ad=0p pd=0u as=0p ps=0u 
-.ends dff
+
+.ENDS dff

technology/scn3me_subm/tech/tech.py

@@ -50,17 +50,18 @@ layer["blockage"]       = 83
 ###################################################
 ##DRC/LVS Rules Setup
 ###################################################
+_lambda_ = 0.3
 
 #technology parameter
 parameter={}
-parameter["min_tx_size"] = 1.2
+parameter["min_tx_size"] = 4*_lambda_
 parameter["beta"] = 2 
 
 drclvs_home=os.environ.get("DRCLVS_HOME")
 
 drc={}
 #grid size is 1/2 a lambda
-drc["grid"]=0.15
+drc["grid"]=0.5*_lambda_
 #DRC/LVS test set_up
 drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
 drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
@@ -68,52 +69,52 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
 
         	      					
 # minwidth_tx with contact (no dog bone transistors)
-drc["minwidth_tx"] = 1.2
-drc["minlength_channel"] = 0.6
+drc["minwidth_tx"] = 4*_lambda_
+drc["minlength_channel"] = 2*_lambda_
 
 # 1.3 Minimum spacing between wells of same type (if both are drawn) 
-drc["well_to_well"] = 1.8
+drc["well_to_well"] = 6*_lambda_
 # 1.4 Minimum spacing between wells of different type (if both are drawn) 
 drc["pwell_to_nwell"] = 0
 # 1.1 Minimum width 
-drc["minwidth_well"] = 3.6
+drc["minwidth_well"] = 12*_lambda_
 
 # 3.1 Minimum width 
-drc["minwidth_poly"] = 0.6
+drc["minwidth_poly"] = 2*_lambda_
 # 3.2 Minimum spacing over active
-drc["poly_to_poly"] = 0.9
+drc["poly_to_poly"] = 3*_lambda_
 # 3.3 Minimum gate extension of active 
-drc["poly_extend_active"] = 0.6
+drc["poly_extend_active"] = 2*_lambda_
 # 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
-drc["poly_to_polycontact"] = 1.2
+drc["poly_to_polycontact"] = 4*_lambda_
 # ??
 drc["active_enclosure_gate"] = 0.0
 # 3.5 Minimum field poly to active 
-drc["poly_to_active"] = 0.3
+drc["poly_to_active"] = _lambda_
 # 3.2.a Minimum spacing over field poly
-drc["poly_to_field_poly"] = 0.9
+drc["poly_to_field_poly"] = 3*_lambda_
 # Not a rule
 drc["minarea_poly"] = 0.0
 
 # ??
-drc["active_to_body_active"] = 1.2  # Fix me
+drc["active_to_body_active"] = 4*_lambda_  # Fix me
 # 2.1 Minimum width 
-drc["minwidth_active"] = 0.9
+drc["minwidth_active"] = 3*_lambda_
 # 2.2 Minimum spacing
-drc["active_to_active"] = 0.9
+drc["active_to_active"] = 3*_lambda_
 # 2.3 Source/drain active to well edge 
-drc["well_enclosure_active"] = 1.8
+drc["well_enclosure_active"] = 6*_lambda_
 # Reserved for asymmetric enclosures
-drc["well_extend_active"] = 1.8
+drc["well_extend_active"] = 6*_lambda_
 # Not a rule
 drc["minarea_active"] = 0.0
 
 # 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width 
-drc["implant_to_channel"] = 0.9
+drc["implant_to_channel"] = 3*_lambda_
 # 4.2 Minimum select overlap of active
-drc["implant_enclosure_active"] = 0.6
+drc["implant_enclosure_active"] = 2*_lambda_
 # 4.3 Minimum select overlap of contact  
-drc["implant_enclosure_contact"] = 0.3
+drc["implant_enclosure_contact"] = _lambda_
 # Not a rule
 drc["implant_to_contact"] = 0
 # Not a rule
@@ -122,70 +123,70 @@ drc["implant_to_implant"] = 0
 drc["minwidth_implant"] = 0
 
 # 6.1 Exact contact size
-drc["minwidth_contact"] = 0.6
+drc["minwidth_contact"] = 2*_lambda_
 # 5.3 Minimum contact spacing
-drc["contact_to_contact"] = 0.9                    
+drc["contact_to_contact"] = 3*_lambda_               
 # 6.2.b Minimum active overlap 
-drc["active_enclosure_contact"] = 0.3
+drc["active_enclosure_contact"] = _lambda_
 # Reserved for asymmetric enclosure
-drc["active_extend_contact"] = 0.3
+drc["active_extend_contact"] = _lambda_
 # 5.2.b Minimum poly overlap 
-drc["poly_enclosure_contact"] = 0.3
+drc["poly_enclosure_contact"] = _lambda_
 # Reserved for asymmetric enclosures
-drc["poly_extend_contact"] = 0.3
+drc["poly_extend_contact"] = _lambda_
 # Reserved for other technologies
-drc["contact_to_gate"] = 0.6
+drc["contact_to_gate"] = 2*_lambda_
 # 5.4 Minimum spacing to gate of transistor
-drc["contact_to_poly"] = 0.6
+drc["contact_to_poly"] = 2*_lambda_
         
 # 7.1 Minimum width 
-drc["minwidth_metal1"] = 0.9
+drc["minwidth_metal1"] = 3*_lambda_
 # 7.2 Minimum spacing 
-drc["metal1_to_metal1"] = 0.9
+drc["metal1_to_metal1"] = 3*_lambda_
 # 7.3 Minimum overlap of any contact 
-drc["metal1_enclosure_contact"] = 0.3
+drc["metal1_enclosure_contact"] = _lambda_
 # Reserved for asymmetric enclosure
-drc["metal1_extend_contact"] = 0.3
+drc["metal1_extend_contact"] = _lambda_
 # 8.3 Minimum overlap by metal1 
-drc["metal1_enclosure_via1"] = 0.3                
+drc["metal1_enclosure_via1"] = _lambda_           
 # Reserve for asymmetric enclosures
-drc["metal1_extend_via1"] = 0.3
+drc["metal1_extend_via1"] = _lambda_
 # Not a rule
 drc["minarea_metal1"] = 0
 
 # 8.1 Exact size 
-drc["minwidth_via1"] = 0.6
+drc["minwidth_via1"] = 2*_lambda_
 # 8.2 Minimum via1 spacing 
-drc["via1_to_via1"] = 0.6
+drc["via1_to_via1"] = 3*_lambda_
 
 # 9.1 Minimum width
-drc["minwidth_metal2"] = 0.9
+drc["minwidth_metal2"] = 3*_lambda_
 # 9.2 Minimum spacing 
-drc["metal2_to_metal2"] = 0.9
+drc["metal2_to_metal2"] = 3*_lambda_
 # 9.3 Minimum overlap of via1 
-drc["metal2_extend_via1"] = 0.3
+drc["metal2_extend_via1"] = _lambda_
 # Reserved for asymmetric enclosures
-drc["metal2_enclosure_via1"] = 0.3
+drc["metal2_enclosure_via1"] = _lambda_
 # 14.3 Minimum overlap by metal2
-drc["metal2_extend_via2"] = 0.3
+drc["metal2_extend_via2"] = _lambda_
 # Reserved for asymmetric enclosures
-drc["metal2_enclosure_via2"] = 0.3
+drc["metal2_enclosure_via2"] = _lambda_
 # Not a rule
 drc["minarea_metal2"] = 0
 
-# 14.2 Exact size
-drc["minwidth_via2"] = 0.6
+# 14.1 Exact size
+drc["minwidth_via2"] = 2*_lambda_
 # 14.2 Minimum spacing
-drc["via2_to_via2"] = 0.9    
+drc["via2_to_via2"] = 3*_lambda_
 
 # 15.1 Minimum width
-drc["minwidth_metal3"] = 1.5
+drc["minwidth_metal3"] = 5*_lambda_
 # 15.2 Minimum spacing to metal3
-drc["metal3_to_metal3"] = 0.9
+drc["metal3_to_metal3"] = 3*_lambda_
 # 15.3 Minimum overlap of via 2
-drc["metal3_extend_via2"] = 0.6
+drc["metal3_extend_via2"] = 2*_lambda_
 # Reserved for asymmetric enclosures
-drc["metal3_enclosure_via2"] = 0.6
+drc["metal3_enclosure_via2"] = 2*_lambda_
 # Not a rule
 drc["minarea_metal3"] = 0
 
@@ -259,12 +260,12 @@ spice["nor2_leakage"] = 1        # Leakage power of 2-input nor in nW
 spice["msflop_leakage"] = 1      # Leakage power of flop in nW
 spice["flop_para_cap"] = 2       # Parasitic Output capacitance in fF
 
-spice["default_event_rate"] = 100           # Default event activity of every gate. MHz
-spice["flop_transisition_prob"] = .5        # Transition probability of inverter.
-spice["inv_transisition_prob"] = .5         # Transition probability of inverter.
-spice["nand2_transisition_prob"] = .1875    # Transition probability of 2-input nand.
-spice["nand3_transisition_prob"] = .1094    # Transition probability of 3-input nand.
-spice["nor2_transisition_prob"] = .1875     # Transition probability of 2-input nor.
+spice["default_event_rate"] = 100         # Default event activity of every gate. MHz
+spice["flop_transition_prob"] = .5        # Transition probability of inverter.
+spice["inv_transition_prob"] = .5         # Transition probability of inverter.
+spice["nand2_transition_prob"] = .1875    # Transition probability of 2-input nand.
+spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input nand.
+spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 ###################################################
 ##END Spice Simulation Parameters
 ###################################################

technology/scn4m_subm/mag_lib/.magicrc

@@ -0,0 +1,5 @@
+path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech
+tech load SCN4M_SUBM.20 -noprompt
+scalegrid 1 4
+set GND gnd
+set VDD vdd

technology/scn4m_subm/mag_lib/cell_6t.mag

@@ -0,0 +1,117 @@
+magic
+tech scmos
+timestamp 1536091415
+<< nwell >>
+rect -8 29 42 51
+<< pwell >>
+rect -8 -8 42 29
+<< ntransistor >>
+rect 7 10 9 18
+rect 29 10 31 18
+rect 10 3 14 5
+rect 24 3 28 5
+<< ptransistor >>
+rect 7 37 11 40
+rect 27 37 31 40
+<< ndiffusion >>
+rect -2 16 7 18
+rect 2 12 7 16
+rect -2 10 7 12
+rect 9 14 10 18
+rect 9 10 14 14
+rect 28 14 29 18
+rect 24 10 29 14
+rect 31 16 36 18
+rect 31 12 32 16
+rect 31 10 36 12
+rect 10 5 14 10
+rect 24 5 28 10
+rect 10 2 14 3
+rect 24 2 28 3
+<< pdiffusion >>
+rect 2 37 7 40
+rect 11 37 12 40
+rect 26 37 27 40
+rect 31 37 32 40
+<< ndcontact >>
+rect -2 12 2 16
+rect 10 14 14 18
+rect 24 14 28 18
+rect 32 12 36 16
+rect 10 -2 14 2
+rect 24 -2 28 2
+<< pdcontact >>
+rect -2 36 2 40
+rect 12 36 16 40
+rect 22 36 26 40
+rect 32 36 36 40
+<< psubstratepcontact >>
+rect -2 22 2 26
+rect 32 22 36 26
+<< nsubstratencontact >>
+rect 32 44 36 48
+<< polysilicon >>
+rect 7 40 11 42
+rect 27 40 31 42
+rect 7 35 11 37
+rect 7 21 9 35
+rect 27 34 31 37
+rect 15 33 31 34
+rect 19 32 31 33
+rect 7 20 21 21
+rect 7 19 24 20
+rect 7 18 9 19
+rect 29 18 31 32
+rect 7 8 9 10
+rect 17 5 21 6
+rect 29 8 31 10
+rect -2 3 10 5
+rect 14 3 24 5
+rect 28 3 36 5
+<< polycontact >>
+rect 15 29 19 33
+rect 21 20 25 24
+rect 17 6 21 10
+<< metal1 >>
+rect -2 44 15 48
+rect 19 44 32 48
+rect -2 40 2 44
+rect 32 40 36 44
+rect 11 36 12 40
+rect 26 36 27 40
+rect -2 26 2 29
+rect -2 16 2 22
+rect 11 18 15 36
+rect 23 24 27 36
+rect 25 20 27 24
+rect 14 14 15 18
+rect 23 18 27 20
+rect 32 26 36 29
+rect 23 14 24 18
+rect 32 16 36 22
+rect -2 6 17 9
+rect 21 6 36 9
+rect -2 5 36 6
+<< m2contact >>
+rect 15 44 19 48
+rect -2 29 2 33
+rect 32 29 36 33
+rect 6 -2 10 2
+rect 20 -2 24 2
+<< metal2 >>
+rect -2 33 2 48
+rect -2 -2 2 29
+rect 6 2 10 48
+rect 24 -2 28 48
+rect 32 33 36 48
+rect 32 -2 36 29
+<< bb >>
+rect 0 0 34 46
+<< labels >>
+rlabel metal2 0 0 0 0 1 gnd
+rlabel metal2 34 0 34 0 1 gnd
+rlabel m2contact 17 46 17 46 5 vdd
+rlabel metal2 8 43 8 43 1 bl
+rlabel metal2 26 43 26 43 1 br
+rlabel metal1 4 7 4 7 1 wl
+<< end >>

technology/scn4m_subm/mag_lib/convertall.sh

@@ -0,0 +1,14 @@
+magic -dnull -noconsole << EOF
+load dff
+gds write dff.gds
+load cell_6t
+gds write cell_6t.gds
+load replica_cell_6t
+gds write replica_cell_6t.gds
+load sense_amp
+gds write sense_amp.gds
+load tri_gate
+gds write tri_gate.gds
+load write_driver
+gds write write_driver.gds
+EOF

technology/scn4m_subm/mag_lib/dff.mag

@@ -0,0 +1,279 @@
+magic
+tech scmos
+timestamp 1536089597
+<< nwell >>
+rect 0 48 109 103
+<< pwell >>
+rect 0 -3 109 48
+<< ntransistor >>
+rect 11 6 13 26
+rect 19 6 21 16
+rect 24 6 26 16
+rect 33 6 35 16
+rect 38 6 40 16
+rect 47 6 49 16
+rect 63 6 65 16
+rect 68 6 70 16
+rect 78 6 80 16
+rect 83 6 85 16
+rect 91 6 93 26
+<< ptransistor >>
+rect 11 54 13 94
+rect 19 74 21 94
+rect 25 74 27 94
+rect 33 74 35 94
+rect 39 74 41 94
+rect 47 74 49 94
+rect 63 74 65 94
+rect 68 74 70 94
+rect 78 84 80 94
+rect 83 84 85 94
+rect 91 54 93 94
+<< ndiffusion >>
+rect 6 25 11 26
+rect 10 6 11 25
+rect 13 25 18 26
+rect 13 6 14 25
+rect 86 25 91 26
+rect 18 6 19 16
+rect 21 6 24 16
+rect 26 15 33 16
+rect 26 6 28 15
+rect 32 6 33 15
+rect 35 6 38 16
+rect 40 15 47 16
+rect 40 6 41 15
+rect 45 6 47 15
+rect 49 15 54 16
+rect 49 6 50 15
+rect 58 15 63 16
+rect 62 6 63 15
+rect 65 6 68 16
+rect 70 15 78 16
+rect 70 6 72 15
+rect 76 6 78 15
+rect 80 6 83 16
+rect 85 6 86 16
+rect 90 6 91 25
+rect 93 25 98 26
+rect 93 6 94 25
+<< pdiffusion >>
+rect 6 93 11 94
+rect 10 54 11 93
+rect 13 55 14 94
+rect 18 74 19 94
+rect 21 74 25 94
+rect 27 93 33 94
+rect 27 74 28 93
+rect 32 74 33 93
+rect 35 74 39 94
+rect 41 93 47 94
+rect 41 74 42 93
+rect 46 74 47 93
+rect 49 93 54 94
+rect 49 74 50 93
+rect 58 93 63 94
+rect 62 74 63 93
+rect 65 74 68 94
+rect 70 93 78 94
+rect 70 74 72 93
+rect 76 84 78 93
+rect 80 84 83 94
+rect 85 93 91 94
+rect 85 84 86 93
+rect 76 74 77 84
+rect 13 54 18 55
+rect 90 54 91 93
+rect 93 93 98 94
+rect 93 54 94 93
+<< ndcontact >>
+rect 6 6 10 25
+rect 14 6 18 25
+rect 28 6 32 15
+rect 41 6 45 15
+rect 50 6 54 15
+rect 58 6 62 15
+rect 72 6 76 15
+rect 86 6 90 25
+rect 94 6 98 25
+<< pdcontact >>
+rect 6 54 10 93
+rect 14 55 18 94
+rect 28 74 32 93
+rect 42 74 46 93
+rect 50 74 54 93
+rect 58 74 62 93
+rect 72 74 76 93
+rect 86 54 90 93
+rect 94 54 98 93
+<< psubstratepcontact >>
+rect 102 6 106 10
+<< nsubstratencontact >>
+rect 102 89 106 93
+<< polysilicon >>
+rect 11 94 13 96
+rect 19 94 21 96
+rect 25 94 27 96
+rect 33 94 35 96
+rect 39 94 41 96
+rect 47 94 49 96
+rect 63 94 65 96
+rect 68 94 70 96
+rect 78 94 80 96
+rect 83 94 85 96
+rect 91 94 93 96
+rect 11 37 13 54
+rect 19 46 21 74
+rect 11 26 13 33
+rect 19 16 21 42
+rect 25 38 27 74
+rect 33 54 35 74
+rect 33 29 35 50
+rect 24 27 35 29
+rect 39 71 41 74
+rect 24 16 26 27
+rect 39 23 41 67
+rect 47 61 49 74
+rect 63 73 65 74
+rect 54 71 65 73
+rect 34 19 35 23
+rect 33 16 35 19
+rect 38 19 39 23
+rect 38 16 40 19
+rect 47 16 49 57
+rect 53 19 55 67
+rect 68 63 70 74
+rect 78 67 80 84
+rect 76 65 80 67
+rect 63 61 70 63
+rect 61 24 63 33
+rect 68 31 70 61
+rect 83 53 85 84
+rect 79 51 85 53
+rect 78 31 80 47
+rect 91 45 93 54
+rect 89 41 93 45
+rect 68 29 75 31
+rect 61 22 70 24
+rect 53 17 65 19
+rect 63 16 65 17
+rect 68 16 70 22
+rect 73 19 75 29
+rect 78 27 79 31
+rect 73 17 80 19
+rect 78 16 80 17
+rect 83 16 85 31
+rect 91 26 93 41
+rect 11 4 13 6
+rect 19 4 21 6
+rect 24 4 26 6
+rect 33 4 35 6
+rect 38 4 40 6
+rect 47 4 49 6
+rect 63 4 65 6
+rect 68 4 70 6
+rect 78 4 80 6
+rect 83 4 85 6
+rect 91 4 93 6
+<< polycontact >>
+rect 17 42 21 46
+rect 10 33 14 37
+rect 31 50 35 54
+rect 25 34 29 38
+rect 39 67 43 71
+rect 45 57 49 61
+rect 30 19 34 23
+rect 39 19 43 23
+rect 53 67 57 71
+rect 59 59 63 63
+rect 74 61 78 65
+rect 59 33 63 37
+rect 77 47 81 51
+rect 85 41 89 45
+rect 79 27 83 31
+<< metal1 >>
+rect 0 97 109 103
+rect 14 94 18 97
+rect 6 93 10 94
+rect 28 93 32 94
+rect 22 74 28 77
+rect 42 93 46 97
+rect 50 93 54 94
+rect 58 93 62 97
+rect 71 93 77 94
+rect 71 74 72 93
+rect 76 74 77 93
+rect 86 93 90 97
+rect 50 71 53 74
+rect 43 68 53 71
+rect 26 57 45 60
+rect 52 60 59 63
+rect 52 54 55 60
+rect 71 56 74 65
+rect 10 50 31 52
+rect 35 51 55 54
+rect 62 53 74 56
+rect 94 93 98 94
+rect 102 93 106 97
+rect 6 49 34 50
+rect 21 43 38 46
+rect 18 34 25 37
+rect 62 37 65 53
+rect 94 51 98 54
+rect 81 48 94 51
+rect 74 41 85 44
+rect 29 34 59 37
+rect 6 25 10 26
+rect 14 25 18 26
+rect 31 23 34 34
+rect 63 34 65 37
+rect 94 31 98 47
+rect 83 28 98 31
+rect 94 25 98 28
+rect 43 19 53 22
+rect 50 16 53 19
+rect 22 15 32 16
+rect 22 13 28 15
+rect 41 15 46 16
+rect 45 6 46 15
+rect 50 15 54 16
+rect 58 15 62 16
+rect 70 15 77 16
+rect 70 13 72 15
+rect 71 6 72 13
+rect 76 6 77 15
+rect 14 3 18 6
+rect 41 3 46 6
+rect 58 3 62 6
+rect 86 3 90 6
+rect 102 3 106 6
+rect 0 -3 109 3
+<< m2contact >>
+rect 22 70 26 74
+rect 70 70 74 74
+rect 22 57 26 61
+rect 6 50 10 54
+rect 38 43 42 47
+rect 14 33 18 37
+rect 94 47 98 51
+rect 70 40 74 44
+rect 6 26 10 30
+rect 22 16 26 20
+rect 70 16 74 20
+<< metal2 >>
+rect 22 61 26 70
+rect 6 30 10 50
+rect 22 20 26 57
+rect 70 44 74 70
+rect 70 20 74 40
+<< bb >>
+rect 0 0 109 100
+<< labels >>
+rlabel m2contact 15 34 15 34 4 clk
+rlabel m2contact 40 45 40 45 4 D
+rlabel m2contact 96 49 96 49 4 Q
+rlabel metal1 32 98 32 98 4 vdd
+rlabel metal1 44 1 44 1 4 gnd
+<< properties >>
+string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000 
+<< end >>

technology/scn4m_subm/mag_lib/replica_cell_6t.mag

@@ -0,0 +1,118 @@
+magic
+tech scmos
+timestamp 1536091380
+<< nwell >>
+rect -8 29 42 51
+<< pwell >>
+rect -8 -8 42 29
+<< ntransistor >>
+rect 7 10 9 18
+rect 29 10 31 18
+rect 10 3 14 5
+rect 24 3 28 5
+<< ptransistor >>
+rect 7 37 11 40
+rect 27 37 31 40
+<< ndiffusion >>
+rect -2 16 7 18
+rect 2 12 7 16
+rect -2 10 7 12
+rect 9 14 10 18
+rect 9 10 14 14
+rect 28 14 29 18
+rect 24 10 29 14
+rect 31 16 36 18
+rect 31 12 32 16
+rect 31 10 36 12
+rect 10 5 14 10
+rect 24 5 28 10
+rect 10 2 14 3
+rect 24 2 28 3
+<< pdiffusion >>
+rect 2 37 7 40
+rect 11 37 12 40
+rect 26 37 27 40
+rect 31 37 32 40
+<< ndcontact >>
+rect -2 12 2 16
+rect 10 14 14 18
+rect 24 14 28 18
+rect 32 12 36 16
+rect 10 -2 14 2
+rect 24 -2 28 2
+<< pdcontact >>
+rect -2 36 2 40
+rect 12 36 16 40
+rect 22 36 26 40
+rect 32 36 36 40
+<< psubstratepcontact >>
+rect -2 22 2 26
+rect 32 22 36 26
+<< nsubstratencontact >>
+rect 32 44 36 48
+<< polysilicon >>
+rect 7 40 11 42
+rect 27 40 31 42
+rect 7 35 11 37
+rect 7 21 9 35
+rect 27 34 31 37
+rect 15 33 31 34
+rect 19 32 31 33
+rect 7 20 21 21
+rect 7 19 24 20
+rect 7 18 9 19
+rect 29 18 31 32
+rect 7 8 9 10
+rect 17 5 21 6
+rect 29 8 31 10
+rect -2 3 10 5
+rect 14 3 24 5
+rect 28 3 36 5
+<< polycontact >>
+rect 15 29 19 33
+rect 21 20 25 24
+rect 17 6 21 10
+<< metal1 >>
+rect -2 44 15 48
+rect 19 44 32 48
+rect -2 40 2 44
+rect 32 40 36 44
+rect 11 36 12 40
+rect 26 36 27 40
+rect -2 26 2 29
+rect 11 22 15 36
+rect 23 24 27 36
+rect -2 18 15 22
+rect 25 20 27 24
+rect -2 16 2 18
+rect 14 14 15 18
+rect 23 18 27 20
+rect 32 26 36 29
+rect 23 14 24 18
+rect 32 16 36 22
+rect -2 6 17 9
+rect 21 6 36 9
+rect -2 5 36 6
+<< m2contact >>
+rect 15 44 19 48
+rect -2 29 2 33
+rect 32 29 36 33
+rect 6 -2 10 2
+rect 20 -2 24 2
+<< metal2 >>
+rect -2 33 2 48
+rect -2 -2 2 29
+rect 6 2 10 48
+rect 24 -2 28 48
+rect 32 33 36 48
+rect 32 -2 36 29
+<< bb >>
+rect 0 0 34 46
+<< labels >>
+rlabel metal2 0 0 0 0 1 gnd
+rlabel metal2 34 0 34 0 1 gnd
+rlabel m2contact 17 46 17 46 5 vdd
+rlabel metal2 8 43 8 43 1 bl
+rlabel metal2 26 43 26 43 1 br
+rlabel metal1 4 7 4 7 1 wl
+<< end >>

technology/scn4m_subm/mag_lib/sense_amp.mag

@@ -0,0 +1,136 @@
+magic
+tech scmos
+timestamp 1536089670
+<< nwell >>
+rect 0 0 40 102
+<< pwell >>
+rect 0 102 40 163
+<< ntransistor >>
+rect 21 130 23 139
+rect 12 108 14 117
+rect 20 108 22 117
+<< ptransistor >>
+rect 12 78 14 96
+rect 20 78 22 96
+rect 11 20 13 44
+rect 27 20 29 44
+<< ndiffusion >>
+rect 20 130 21 139
+rect 23 130 24 139
+rect 11 108 12 117
+rect 14 108 15 117
+rect 19 108 20 117
+rect 22 108 23 117
+<< pdiffusion >>
+rect 7 94 12 96
+rect 11 80 12 94
+rect 7 78 12 80
+rect 14 94 20 96
+rect 14 80 15 94
+rect 19 80 20 94
+rect 14 78 20 80
+rect 22 94 27 96
+rect 22 80 23 94
+rect 22 78 27 80
+rect 10 20 11 44
+rect 13 20 14 44
+rect 26 20 27 44
+rect 29 20 30 44
+<< ndcontact >>
+rect 16 130 20 139
+rect 24 130 28 139
+rect 7 108 11 117
+rect 15 108 19 117
+rect 23 108 27 117
+<< pdcontact >>
+rect 7 80 11 94
+rect 15 80 19 94
+rect 23 80 27 94
+rect 6 20 10 44
+rect 14 20 18 44
+rect 22 20 26 44
+rect 30 20 34 44
+<< psubstratepcontact >>
+rect 32 137 36 141
+<< nsubstratencontact >>
+rect 27 70 31 74
+<< polysilicon >>
+rect 21 139 23 149
+rect 21 129 23 130
+rect 3 127 23 129
+rect 3 47 5 127
+rect 12 122 34 124
+rect 12 117 14 122
+rect 20 117 22 119
+rect 12 96 14 108
+rect 20 96 22 108
+rect 32 105 34 122
+rect 30 101 34 105
+rect 12 76 14 78
+rect 20 69 22 78
+rect 13 67 22 69
+rect 9 55 11 65
+rect 32 55 34 101
+rect 33 51 34 55
+rect 3 45 13 47
+rect 11 44 13 45
+rect 27 44 29 46
+rect 11 19 13 20
+rect 27 19 29 20
+rect 11 17 29 19
+<< polycontact >>
+rect 20 149 24 153
+rect 26 101 30 105
+rect 9 65 13 69
+rect 9 51 13 55
+rect 29 51 33 55
+<< metal1 >>
+rect -2 149 20 153
+rect 24 149 36 153
+rect 28 133 32 137
+rect 16 117 19 130
+rect 7 94 11 108
+rect 23 105 27 108
+rect 23 101 26 105
+rect 7 69 11 80
+rect 15 94 19 96
+rect 15 78 19 80
+rect 23 94 27 101
+rect 23 78 27 80
+rect 15 75 18 78
+rect 15 74 31 75
+rect 15 72 27 74
+rect 7 65 9 69
+rect 6 44 9 54
+rect 33 51 34 55
+rect 31 44 34 51
+rect 3 20 6 23
+rect 3 15 7 20
+<< m2contact >>
+rect 32 133 36 137
+rect 27 66 31 70
+rect 13 44 17 48
+rect 22 44 26 48
+rect 3 11 7 15
+<< metal2 >>
+rect 10 48 14 163
+rect 20 48 24 163
+rect 32 129 36 133
+rect 27 62 31 66
+rect 10 44 13 48
+rect 20 44 22 48
+rect 3 0 7 11
+rect 10 0 14 44
+rect 20 0 24 44
+<< bb >>
+rect 0 0 34 163
+<< labels >>
+flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en
+rlabel metal2 34 131 34 131 1 gnd
+rlabel metal2 29 64 29 64 1 vdd
+rlabel metal2 12 161 12 161 5 bl
+rlabel metal2 22 161 22 161 5 br
+rlabel metal2 5 3 5 3 1 dout
+<< properties >>
+string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000 
+<< end >>

technology/scn4m_subm/mag_lib/tri_gate.mag

@@ -0,0 +1,98 @@
+magic
+tech scmos
+timestamp 1536089695
+<< nwell >>
+rect -2 45 38 73
+<< pwell >>
+rect -2 0 38 45
+<< ntransistor >>
+rect 9 27 11 31
+rect 17 27 19 31
+rect 25 27 27 31
+<< ptransistor >>
+rect 9 53 11 61
+rect 17 53 19 61
+rect 25 53 27 61
+<< ndiffusion >>
+rect 8 27 9 31
+rect 11 27 12 31
+rect 16 27 17 31
+rect 19 27 20 31
+rect 24 27 25 31
+rect 27 27 28 31
+<< pdiffusion >>
+rect 8 53 9 61
+rect 11 53 12 61
+rect 16 53 17 61
+rect 19 53 20 61
+rect 24 53 25 61
+rect 27 53 28 61
+<< ndcontact >>
+rect 4 27 8 31
+rect 12 27 16 31
+rect 20 27 24 31
+rect 28 27 32 31
+<< pdcontact >>
+rect 4 53 8 61
+rect 12 53 16 61
+rect 20 53 24 61
+rect 28 53 32 61
+<< psubstratepcontact >>
+rect 12 19 16 23
+<< nsubstratencontact >>
+rect 12 65 16 69
+<< polysilicon >>
+rect 25 63 35 65
+rect 9 61 11 63
+rect 17 61 19 63
+rect 25 61 27 63
+rect 9 50 11 53
+rect 9 31 11 46
+rect 17 42 19 53
+rect 25 51 27 53
+rect 17 31 19 38
+rect 25 31 27 33
+rect 9 25 11 27
+rect 17 25 19 27
+rect 25 16 27 27
+rect 33 8 35 63
+rect 32 6 35 8
+<< polycontact >>
+rect 9 46 13 50
+rect 16 38 20 42
+rect 25 12 29 16
+rect 28 4 32 8
+<< metal1 >>
+rect 16 65 23 69
+rect 12 61 16 65
+rect 3 53 4 61
+rect 3 42 6 53
+rect 13 46 15 50
+rect 3 38 16 42
+rect 3 31 6 38
+rect 29 31 32 53
+rect 3 27 4 31
+rect 12 23 16 27
+rect 16 19 24 23
+rect 0 12 25 16
+rect 29 12 36 16
+rect 0 4 28 8
+rect 32 4 36 8
+<< m2contact >>
+rect 23 65 27 69
+rect 15 46 19 50
+rect 25 34 29 38
+rect 24 19 28 23
+<< metal2 >>
+rect 15 34 25 38
+rect 15 0 19 34
+<< bb >>
+rect 0 0 34 73
+<< labels >>
+rlabel metal1 0 12 0 12 3 en
+rlabel metal1 0 4 0 4 2 en_bar
+rlabel metal2 16 1 16 1 1 out
+rlabel m2contact 26 21 26 21 1 gnd
+rlabel m2contact 25 67 25 67 1 vdd
+rlabel m2contact 17 48 17 48 1 in
+<< end >>

technology/scn4m_subm/mag_lib/write_driver.mag

@@ -0,0 +1,224 @@
+magic
+tech scmos
+timestamp 1536089714
+<< nwell >>
+rect -3 101 37 138
+rect -3 0 37 51
+<< pwell >>
+rect -3 138 37 202
+rect -3 51 37 101
+<< ntransistor >>
+rect 9 177 11 189
+rect 17 177 19 189
+rect 15 162 27 164
+rect 9 144 11 148
+rect 17 144 19 148
+rect 10 82 12 89
+rect 18 82 20 89
+rect 8 57 10 64
+rect 16 57 18 64
+rect 24 60 26 64
+<< ptransistor >>
+rect 9 125 11 132
+rect 17 125 19 132
+rect 10 107 12 114
+rect 18 107 20 114
+rect 8 38 10 45
+rect 16 38 18 45
+rect 24 38 26 45
+<< ndiffusion >>
+rect 8 177 9 189
+rect 11 177 12 189
+rect 16 177 17 189
+rect 19 177 20 189
+rect 15 164 27 165
+rect 15 161 27 162
+rect 12 157 15 160
+rect 12 156 16 157
+rect 8 144 9 148
+rect 11 144 12 148
+rect 16 144 17 148
+rect 19 144 20 148
+rect 9 82 10 89
+rect 12 82 13 89
+rect 17 82 18 89
+rect 20 82 21 89
+rect 25 82 26 86
+rect 7 57 8 64
+rect 10 57 11 64
+rect 15 57 16 64
+rect 18 57 19 64
+rect 23 60 24 64
+rect 26 60 27 64
+<< pdiffusion >>
+rect 8 125 9 132
+rect 11 125 12 132
+rect 16 125 17 132
+rect 19 125 20 132
+rect 12 122 16 125
+rect 9 107 10 114
+rect 12 107 13 114
+rect 17 107 18 114
+rect 20 107 21 114
+rect 7 38 8 45
+rect 10 38 11 45
+rect 15 38 16 45
+rect 18 38 19 45
+rect 23 38 24 45
+rect 26 38 27 45
+rect 3 35 7 38
+<< ndcontact >>
+rect 4 177 8 189
+rect 12 177 16 189
+rect 20 177 24 189
+rect 15 165 27 169
+rect 15 157 27 161
+rect 4 144 8 148
+rect 12 144 16 148
+rect 20 144 24 148
+rect 5 82 9 89
+rect 13 82 17 89
+rect 21 82 25 89
+rect 3 57 7 64
+rect 11 57 15 64
+rect 19 57 23 64
+rect 27 60 31 64
+<< pdcontact >>
+rect 4 125 8 132
+rect 12 125 16 132
+rect 20 125 24 132
+rect 5 107 9 114
+rect 13 107 17 114
+rect 21 107 25 114
+rect 3 38 7 45
+rect 11 38 15 45
+rect 19 38 23 45
+rect 27 38 31 45
+<< psubstratepcontact >>
+rect 12 152 16 156
+rect 26 82 30 86
+<< nsubstratencontact >>
+rect 12 118 16 122
+rect 3 31 7 35
+<< polysilicon >>
+rect 9 194 30 196
+rect 9 189 11 194
+rect 17 189 19 191
+rect 28 185 30 194
+rect 9 175 11 177
+rect 17 172 19 177
+rect 6 170 19 172
+rect 6 167 8 170
+rect 13 162 15 164
+rect 27 162 33 164
+rect 9 148 11 150
+rect 17 148 19 150
+rect 9 132 11 144
+rect 17 132 19 144
+rect 9 124 11 125
+rect 2 122 11 124
+rect 17 124 19 125
+rect 17 122 28 124
+rect 2 75 4 122
+rect 10 114 12 116
+rect 18 114 20 116
+rect 10 89 12 107
+rect 18 106 20 107
+rect 16 104 20 106
+rect 16 92 18 104
+rect 26 100 28 122
+rect 27 96 28 100
+rect 16 90 20 92
+rect 18 89 20 90
+rect 10 81 12 82
+rect 10 79 13 81
+rect 2 71 3 75
+rect 11 71 13 79
+rect 18 79 20 82
+rect 18 77 23 79
+rect 31 71 33 162
+rect 11 69 33 71
+rect 11 67 13 69
+rect 8 65 13 67
+rect 8 64 10 65
+rect 16 64 18 66
+rect 24 64 26 66
+rect 8 45 10 57
+rect 16 52 18 57
+rect 24 52 26 60
+rect 16 50 26 52
+rect 16 45 18 50
+rect 24 45 26 50
+rect 8 28 10 38
+rect 16 14 18 38
+rect 24 36 26 38
+<< polycontact >>
+rect 28 181 32 185
+rect 4 163 8 167
+rect 23 96 27 100
+rect 3 71 7 75
+rect 23 75 27 79
+rect 7 24 11 28
+rect 15 10 19 14
+<< metal1 >>
+rect 5 192 10 196
+rect 5 189 8 192
+rect 32 181 33 185
+rect 13 169 16 177
+rect 13 165 15 169
+rect 4 148 8 163
+rect 12 157 15 161
+rect 12 156 16 157
+rect 12 148 16 152
+rect 4 132 8 144
+rect 20 142 24 144
+rect 30 142 33 181
+rect 20 138 33 142
+rect 20 132 24 138
+rect 12 122 16 125
+rect 13 114 17 118
+rect 5 104 9 107
+rect 21 104 25 107
+rect 5 101 25 104
+rect 5 89 9 101
+rect 21 100 25 101
+rect 21 96 23 100
+rect 25 82 26 90
+rect 4 64 7 71
+rect 27 64 31 79
+rect 3 51 7 57
+rect 3 48 15 51
+rect 11 45 15 48
+rect 27 45 31 60
+rect 3 35 7 38
+rect 19 35 23 38
+rect 7 31 19 35
+rect 0 24 7 28
+rect 11 24 36 28
+<< m2contact >>
+rect 10 192 14 196
+rect 20 189 24 193
+rect 23 153 27 157
+rect 16 118 20 122
+rect 26 86 30 90
+rect 19 64 23 68
+rect 19 31 23 35
+rect 15 6 19 10
+<< metal2 >>
+rect 10 196 14 202
+rect 20 193 24 202
+rect 20 177 24 189
+rect 15 0 19 6
+<< bb >>
+rect 0 0 34 202
+<< labels >>
+rlabel metal2 15 1 15 1 1 din
+rlabel metal1 2 25 2 25 3 en
+rlabel metal2 12 200 12 200 5 bl
+rlabel metal2 22 200 22 200 5 br
+rlabel m2contact 21 66 21 66 1 gnd
+rlabel m2contact 28 88 28 88 1 gnd
+rlabel m2contact 21 33 21 33 1 vdd
+rlabel m2contact 18 120 18 120 1 vdd
+rlabel m2contact 25 155 25 155 1 gnd
+<< end >>

technology/scn4m_subm/models/ff/nmos.sp

@@ -0,0 +1,10 @@
+*********************************************
+* Transistor Models
+* Note: These models are approximate 
+*       and should be substituted with actual
+*       models from MOSIS or SCN4ME
+*********************************************
+
+.MODEL n NMOS (LEVEL=49 VTHO=0.669845
++ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0)
+

technology/scn4m_subm/models/ff/pmos.sp

@@ -0,0 +1,9 @@
+*********************************************
+* Transistor Models
+* Note: These models are approximate 
+*       and should be substituted with actual
+*       models from MOSIS or SCN4ME
+*********************************************
+
+.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
++ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)

technology/scn4m_subm/models/nom/nmos.sp

@@ -0,0 +1,9 @@
+*********************************************
+* Transistor Models
+* Note: These models are approximate 
+*       and should be substituted with actual
+*       models from MOSIS or SCN4ME
+*********************************************
+
+.MODEL n NMOS (LEVEL=49 VTHO=0.669845
++ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0)