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Initial two port bank in SCMOS

This commit is contained in:
Matt Guthaus 2018-11-13 16:05:22 -08:00
parent 732f35a362
commit aa779a7f82
13 changed files with 620 additions and 391 deletions
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854
compiler/modules/bank.py
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File diff suppressed because it is too large Load Diff

12
compiler/modules/bank_select.py
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@ -27,12 +27,12 @@ class bank_select(design.design):
def create_netlist(self):
self.add_pins()
self.add_modules()
self.create_modules()
self.create_instances()
def create_layout(self):
self.calculate_module_offsets()
self.place_modules()
self.route_modules()
self.place_instances()
self.route_instances()
self.DRC_LVS()
@ -99,7 +99,7 @@ class bank_select(design.design):
self.height = self.yoffset_maxpoint + 2*self.m1_pitch
self.width = self.xoffset_inv + self.inv4x.width
def create_modules(self):
def create_instances(self):
self.bank_sel_inv=self.add_inst(name="bank_sel_inv",
mod=self.inv_sel)
@ -152,7 +152,7 @@ class bank_select(design.design):
"vdd",
"gnd"])
def place_modules(self):
def place_instances(self):
# bank select inverter
self.bank_select_inv_position = vector(self.xoffset_bank_sel_inv, 0)
@ -195,7 +195,7 @@ class bank_select(design.design):
mirror=mirror)
def route_modules(self):
def route_instances(self):
# bank_sel is vertical wire
bank_sel_inv_pin = self.bank_sel_inv.get_pin("A")

4
compiler/modules/bitcell_array.py
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@ -34,7 +34,7 @@ class bitcell_array(design.design):
""" Create and connect the netlist """
self.add_modules()
self.add_pins()
self.create_modules()
self.create_instances()
def create_layout(self):
@ -85,7 +85,7 @@ class bitcell_array(design.design):
self.cell = self.mod_bitcell()
self.add_mod(self.cell)
def create_modules(self):
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):

12
compiler/modules/control_logic.py
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@ -41,12 +41,12 @@ class control_logic(design.design):
self.setup_signal_busses()
self.add_pins()
self.add_modules()
self.create_modules()
self.create_instances()
def create_layout(self):
""" Create layout and route between modules """
self.route_rails()
self.place_modules()
self.place_instances()
self.route_all()
#self.add_lvs_correspondence_points()
@ -155,8 +155,8 @@ class control_logic(design.design):
self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height)
def create_modules(self):
""" Create all the modules """
def create_instances(self):
""" Create all the instances """
self.create_dffs()
self.create_clk_row()
if (self.port_type == "rw") or (self.port_type == "w"):
@ -167,8 +167,8 @@ class control_logic(design.design):
self.create_rbl()
def place_modules(self):
""" Place all the modules """
def place_instances(self):
""" Place all the instances """
# Keep track of all right-most instances to determine row boundary
# and add the vdd/gnd pins
self.row_end_inst = []

8
compiler/modules/dff_buf.py
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@ -36,13 +36,13 @@ class dff_buf(design.design):
def create_netlist(self):
self.add_modules()
self.add_pins()
self.create_modules()
self.create_instances()
def create_layout(self):
self.width = self.dff.width + self.inv1.width + self.inv2.width
self.height = self.dff.height
self.place_modules()
self.place_instances()
self.route_wires()
self.add_layout_pins()
self.DRC_LVS()
@ -70,7 +70,7 @@ class dff_buf(design.design):
self.add_pin("vdd")
self.add_pin("gnd")
def create_modules(self):
def create_instances(self):
self.dff_inst=self.add_inst(name="dff_buf_dff",
mod=self.dff)
self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
@ -83,7 +83,7 @@ class dff_buf(design.design):
mod=self.inv2)
self.connect_inst(["Qb", "Q", "vdd", "gnd"])
def place_modules(self):
def place_instances(self):
# Add the DFF
self.dff_inst.place(vector(0,0))

4
compiler/modules/hierarchical_predecode.py
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@ -31,8 +31,8 @@ class hierarchical_predecode(design.design):
self.add_pin("vdd")
self.add_pin("gnd")
def create_modules(self):
""" Create the INV and NAND gate """
def add_modules(self):
""" Add the INV and NAND gate modules """
self.inv = pinv()
self.add_mod(self.inv)

2
compiler/modules/hierarchical_predecode2x4.py
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@ -18,7 +18,7 @@ class hierarchical_predecode2x4(hierarchical_predecode):
def create_netlist(self):
self.add_pins()
self.create_modules()
self.add_modules()
self.create_input_inverters()
self.create_output_inverters()
connections =[["inbar_0", "inbar_1", "Z_0", "vdd", "gnd"],

2
compiler/modules/hierarchical_predecode3x8.py
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@ -18,7 +18,7 @@ class hierarchical_predecode3x8(hierarchical_predecode):
def create_netlist(self):
self.add_pins()
self.create_modules()
self.add_modules()
self.create_input_inverters()
self.create_output_inverters()
connections=[["inbar_0", "inbar_1", "inbar_2", "Z_0", "vdd", "gnd"],

8
compiler/modules/multibank.py
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@ -54,8 +54,8 @@ class multibank(design.design):
self.compute_sizes()
self.add_pins()
self.create_modules()
self.add_modules()
self.create_instances()
self.setup_layout_constraints()
# FIXME: Move this to the add modules function
@ -111,7 +111,7 @@ class multibank(design.design):
self.route_supplies()
def add_modules(self):
def create_instances(self):
""" Add modules. The order should not matter! """
# Above the bitcell array
@ -175,8 +175,8 @@ class multibank(design.design):
def create_modules(self):
""" Create all the modules using the class loader """
def add_modules(self):
""" Add all the modules using the class loader """
self.tri = self.mod_tri_gate()
self.bitcell = self.mod_bitcell()

8
compiler/modules/replica_bitline.py
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@ -29,11 +29,11 @@ class replica_bitline(design.design):
def create_netlist(self):
self.add_modules()
self.add_pins()
self.create_modules()
self.create_instances()
def create_layout(self):
self.calculate_module_offsets()
self.place_modules()
self.place_instances()
self.route()
self.add_layout_pins()
@ -104,7 +104,7 @@ class replica_bitline(design.design):
self.access_tx = ptx(tx_type="pmos")
self.add_mod(self.access_tx)
def create_modules(self):
def create_instances(self):
""" Create all of the module instances in the logical netlist """
# This is the threshold detect inverter on the output of the RBL
@ -152,7 +152,7 @@ class replica_bitline(design.design):
self.wl_list = self.rbl.cell.list_all_wl_names()
self.bl_list = self.rbl.cell.list_all_bl_names()
def place_modules(self):
def place_instances(self):
""" Add all of the module instances in the logical netlist """
# This is the threshold detect inverter on the output of the RBL

7
compiler/modules/wordline_driver.py
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@ -129,16 +129,15 @@ class wordline_driver(design.design):
nand2_xoffset = inv1_xoffset + self.inv.width
inv2_xoffset = nand2_xoffset + self.nand2.width
self.width = inv2_xoffset + self.inv.height
driver_height = self.inv.height
self.width = inv2_xoffset + self.inv.width
self.height = self.inv.height * self.rows
for row in range(self.rows):
if (row % 2):
y_offset = driver_height*(row + 1)
y_offset = self.inv.height*(row + 1)
inst_mirror = "MX"
else:
y_offset = driver_height*row
y_offset = self.inv.height*row
inst_mirror = "R0"
inv1_offset = [inv1_xoffset, y_offset]

60
compiler/sram_1bank.py
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@ -34,14 +34,14 @@ class sram_1bank(sram_base):
self.bank_inst=self.create_bank(0)
self.control_logic_inst = self.create_control_logic()
self.control_logic_insts = self.create_control_logic()
self.row_addr_dff_inst = self.create_row_addr_dff()
self.row_addr_dff_insts = self.create_row_addr_dff()
if self.col_addr_dff:
self.col_addr_dff_inst = self.create_col_addr_dff()
self.col_addr_dff_insts = self.create_col_addr_dff()
self.data_dff_inst = self.create_data_dff()
self.data_dff_insts = self.create_data_dff()
def place_modules(self):
"""
@ -58,14 +58,14 @@ class sram_1bank(sram_base):
# The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
# up to the row address DFFs.
for port in self.all_ports:
control_pos = vector(-self.control_logic.width - 2*self.m2_pitch,
self.bank.bank_center.y - self.control_logic.control_logic_center.y)
self.control_logic_inst[port].place(control_pos)
control_pos = vector(-self.control_logic_rw.width - 2*self.m2_pitch,
self.bank.bank_center.y - self.control_logic_rw.control_logic_center.y)
self.control_logic_insts[port].place(control_pos)
# The row address bits are placed above the control logic aligned on the right.
row_addr_pos = vector(self.control_logic_inst[0].rx() - self.row_addr_dff.width,
self.control_logic_inst[0].uy())
self.row_addr_dff_inst[port].place(row_addr_pos)
row_addr_pos = vector(self.control_logic_insts[0].rx() - self.row_addr_dff.width,
self.control_logic_insts[0].uy())
self.row_addr_dff_insts[port].place(row_addr_pos)
# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
data_gap = -self.m2_pitch*(self.word_size+1)
@ -75,7 +75,7 @@ class sram_1bank(sram_base):
if self.col_addr_dff:
col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width,
data_gap - self.col_addr_dff.height)
self.col_addr_dff_inst[port].place(col_addr_pos)
self.col_addr_dff_insts[port].place(col_addr_pos)
# Add the data flops below the bank to the right of the center of bank:
# This relies on the center point of the bank:
@ -84,7 +84,7 @@ class sram_1bank(sram_base):
# sense amps.
data_pos = vector(self.bank.bank_center.x,
data_gap - self.data_dff.height)
self.data_dff_inst[port].place(data_pos)
self.data_dff_insts[port].place(data_pos)
# two supply rails are already included in the bank, so just 2 here.
# self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
@ -97,7 +97,7 @@ class sram_1bank(sram_base):
for port in self.all_ports:
# Connect the control pins as inputs
for signal in self.control_logic_inputs[port] + ["clk"]:
self.copy_layout_pin(self.control_logic_inst[port], signal, signal+"{}".format(port))
self.copy_layout_pin(self.control_logic_insts[port], signal, signal+"{}".format(port))
if port in self.read_ports:
for bit in range(self.word_size):
@ -105,14 +105,14 @@ class sram_1bank(sram_base):
# Lower address bits
for bit in range(self.col_addr_size):
self.copy_layout_pin(self.col_addr_dff_inst[port], "din_{}".format(bit),"ADDR{0}[{1}]".format(port,bit))
self.copy_layout_pin(self.col_addr_dff_insts[port], "din_{}".format(bit),"ADDR{0}[{1}]".format(port,bit))
# Upper address bits
for bit in range(self.row_addr_size):
self.copy_layout_pin(self.row_addr_dff_inst[port], "din_{}".format(bit),"ADDR{0}[{1}]".format(port,bit+self.col_addr_size))
self.copy_layout_pin(self.row_addr_dff_insts[port], "din_{}".format(bit),"ADDR{0}[{1}]".format(port,bit+self.col_addr_size))
if port in self.write_ports:
for bit in range(self.word_size):
self.copy_layout_pin(self.data_dff_inst[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit))
self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit))
def route(self):
""" Route a single bank SRAM """
@ -135,7 +135,7 @@ class sram_1bank(sram_base):
# This is the actual input to the SRAM
for port in self.all_ports:
self.copy_layout_pin(self.control_logic_inst[port], "clk", "clk{}".format(port))
self.copy_layout_pin(self.control_logic_insts[port], "clk", "clk{}".format(port))
# Connect all of these clock pins to the clock in the central bus
# This is something like a "spine" clock distribution. The two spines
@ -147,23 +147,23 @@ class sram_1bank(sram_base):
bank_clk_buf_bar_pos = bank_clk_buf_bar_pin.center()
if self.col_addr_dff:
dff_clk_pin = self.col_addr_dff_inst[port].get_pin("clk")
dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk")
dff_clk_pos = dff_clk_pin.center()
mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y)
self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos])
data_dff_clk_pin = self.data_dff_inst[port].get_pin("clk")
data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
data_dff_clk_pos = data_dff_clk_pin.center()
mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y)
self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos])
# This uses a metal2 track to the right of the control/row addr DFF
# to route vertically.
control_clk_buf_pin = self.control_logic_inst[port].get_pin("clk_buf")
control_clk_buf_pin = self.control_logic_insts[port].get_pin("clk_buf")
control_clk_buf_pos = control_clk_buf_pin.rc()
row_addr_clk_pin = self.row_addr_dff_inst[port].get_pin("clk")
row_addr_clk_pin = self.row_addr_dff_insts[port].get_pin("clk")
row_addr_clk_pos = row_addr_clk_pin.rc()
mid1_pos = vector(self.row_addr_dff_inst[port].rx() + self.m2_pitch,
mid1_pos = vector(self.row_addr_dff_insts[port].rx() + self.m2_pitch,
row_addr_clk_pos.y)
mid2_pos = vector(mid1_pos.x,
control_clk_buf_pos.y)
@ -176,7 +176,7 @@ class sram_1bank(sram_base):
""" Route the outputs from the control logic module """
for port in self.all_ports:
for signal in self.control_logic_outputs[port]:
src_pin = self.control_logic_inst[port].get_pin(signal)
src_pin = self.control_logic_insts[port].get_pin(signal)
dest_pin = self.bank_inst.get_pin(signal+"{}".format(port))
self.connect_rail_from_left_m2m3(src_pin, dest_pin)
self.add_via_center(layers=("metal1","via1","metal2"),
@ -190,7 +190,7 @@ class sram_1bank(sram_base):
for bit in range(self.row_addr_size):
flop_name = "dout_{}".format(bit)
bank_name = "addr{0}_{1}".format(port,bit+self.col_addr_size)
flop_pin = self.row_addr_dff_inst[port].get_pin(flop_name)
flop_pin = self.row_addr_dff_insts[port].get_pin(flop_name)
bank_pin = self.bank_inst.get_pin(bank_name)
flop_pos = flop_pin.center()
bank_pos = bank_pin.center()
@ -206,13 +206,13 @@ class sram_1bank(sram_base):
bus_names = ["addr_{}".format(x) for x in range(self.col_addr_size)]
col_addr_bus_offsets = self.create_horizontal_bus(layer="metal1",
pitch=self.m1_pitch,
offset=self.col_addr_dff_inst[port].ul() + vector(0, self.m1_pitch),
offset=self.col_addr_dff_insts[port].ul() + vector(0, self.m1_pitch),
names=bus_names,
length=self.col_addr_dff_inst[port].width)
length=self.col_addr_dff_insts[port].width)
dff_names = ["dout_{}".format(x) for x in range(self.col_addr_size)]
data_dff_map = zip(dff_names, bus_names)
self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_inst[port], col_addr_bus_offsets)
self.connect_horizontal_bus(data_dff_map, self.col_addr_dff_insts[port], col_addr_bus_offsets)
bank_names = ["addr{0}_{1}".format(port,x) for x in range(self.col_addr_size)]
data_bank_map = zip(bank_names, bus_names)
@ -223,13 +223,13 @@ class sram_1bank(sram_base):
""" Connect the output of the data flops to the write driver """
# This is where the channel will start (y-dimension at least)
for port in self.write_ports:
offset = self.data_dff_inst[port].ul() + vector(0, 2*self.m1_pitch)
offset = self.data_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
dff_names = ["dout_{}".format(x) for x in range(self.word_size)]
bank_names = ["din{0}_{1}".format(port,x) for x in range(self.word_size)]
route_map = list(zip(bank_names, dff_names))
dff_pins = {key: self.data_dff_inst[port].get_pin(key) for key in dff_names }
dff_pins = {key: self.data_dff_insts[port].get_pin(key) for key in dff_names }
bank_pins = {key: self.bank_inst.get_pin(key) for key in bank_names }
# Combine the dff and bank pins into a single dictionary of pin name to pin.
all_pins = {**dff_pins, **bank_pins}
@ -245,7 +245,7 @@ class sram_1bank(sram_base):
"""
for n in self.control_logic_outputs[0]:
pin = self.control_logic_inst[0].get_pin(n)
pin = self.control_logic_insts[0].get_pin(n)
self.add_label(text=n,
layer=pin.layer,
offset=pin.center())

30
compiler/sram_base.py
View File

@ -216,20 +216,24 @@ class sram_base(design):
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell = self.mod_bitcell()
#c = reload(__import__(OPTS.control_logic))
#self.mod_control_logic = getattr(c, OPTS.control_logic)
c = reload(__import__(OPTS.control_logic))
self.mod_control_logic = getattr(c, OPTS.control_logic)
from control_logic import control_logic
# Create the control logic module for each port type
if OPTS.num_rw_ports>0:
self.control_logic = self.control_logic_rw = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="rw")
if len(self.readwrite_ports)>0:
self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
port_type="rw")
self.add_mod(self.control_logic_rw)
if OPTS.num_w_ports>0:
self.control_logic_w = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="w")
if len(self.write_ports)>0:
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
port_type="w")
self.add_mod(self.control_logic_w)
if OPTS.num_r_ports>0:
self.control_logic_r = control_logic(num_rows=self.num_rows, words_per_row=self.words_per_row, port_type="r")
if len(self.read_ports)>0:
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
port_type="r")
self.add_mod(self.control_logic_r)
# Create the address and control flops (but not the clk)
@ -382,7 +386,8 @@ class sram_base(design):
def create_control_logic(self):
""" Add and place control logic """
""" Add control logic instances """
insts = []
for port in self.all_ports:
if port in self.readwrite_ports:
@ -392,8 +397,7 @@ class sram_base(design):
else:
mod = self.control_logic_r
insts.append(self.add_inst(name="control{}".format(port),
mod=mod))
insts.append(self.add_inst(name="control{}".format(port), mod=mod))
temp = ["csb{}".format(port)]
if port in self.readwrite_ports: