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Change RBL size to 50% of row size.

This commit is contained in:
Matt Guthaus 2018-10-11 10:39:24 -07:00
parent f7d1df6ca7
commit 297ea81060
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/control_logic.py
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@ -95,7 +95,7 @@ class control_logic(design.design):
# FIXME: These should be tuned according to the size!
delay_stages = 4 # Must be non-inverting
delay_fanout = 3 # This can be anything >=2
bitcell_loads = int(math.ceil(self.num_rows / 5.0))
bitcell_loads = int(math.ceil(self.num_rows / 2.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port_type)
self.add_mod(self.replica_bitline)