mirror of https://github.com/VLSIDA/OpenRAM.git
Bitcell and bitcell array can be named the same.
This commit is contained in:
parent
5e0eb609da
commit
e040fd12f9
|
|
@ -36,6 +36,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
|
|||
# aren't unique
|
||||
ok_list = ['contact',
|
||||
'ptx',
|
||||
'pbitcell',
|
||||
'bitcell',
|
||||
'sram',
|
||||
'hierarchical_predecode2x4',
|
||||
'hierarchical_predecode3x8']
|
||||
|
|
|
|||
Loading…
Reference in New Issue