mirror of https://github.com/VLSIDA/OpenRAM.git
Add the minimum pin enclosure that has DRC correct pin connections.
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94e5050513
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@ -624,8 +624,6 @@ class router:
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# Blockages will be a super-set of pins since it uses the inflated pin shape.
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blockage_in_tracks = self.convert_blockage(pin)
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blockage_set.update(blockage_in_tracks)
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debug.info(2," .pins {}".format(pin_set))
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debug.info(2," .blocks {}".format(blockage_set))
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# If we have a blockage, we must remove the grids
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# Remember, this excludes the pin blockages already
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@ -839,7 +837,7 @@ class router:
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self.write_debug_gds("pin_debug.gds", True)
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#self.write_debug_gds("pin_debug.gds", True)
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def compute_enclosure(self, pin, enclosure):
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"""
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@ -98,8 +98,6 @@ class supply_router(router):
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return True
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def route_simple_overlaps(self, pin_name):
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