Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

compiler/base/hierarchy_layout.py

@@ -123,7 +123,8 @@ class layout(lef.lef):
         """Adds an instance of a mod to this module"""
         self.insts.append(geometry.instance(name, mod, offset, mirror, rotate))
         debug.info(3, "adding instance {}".format(self.insts[-1]))
-        debug.info(4, "instance list: " + ",".join(x.name for x in self.insts))
+        # This is commented out for runtime reasons
+        #debug.info(4, "instance list: " + ",".join(x.name for x in self.insts))
         return self.insts[-1]
 
     def get_inst(self, name):

compiler/example_config_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 2
 num_words = 16
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

compiler/example_config_scn4m_subm.py

@@ -1,8 +1,7 @@
 word_size = 2
 num_words = 16
-num_banks = 1
 
-tech_name = "scn3me_subm"
+tech_name = "scn4m_subm"
 process_corners = ["TT"]
 supply_voltages = [ 5.0 ]
 temperatures = [ 25 ]

compiler/globals.py

@@ -74,10 +74,12 @@ def print_banner():
     print("|=========" + name.center(60) + "=========|")
     print("|=========" + " ".center(60) + "=========|")
     print("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
-    print("|=========" + "University of California Santa Cruz CE Department".center(60) + "=========|")
+    print("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
+    print("|=========" + "University of California Santa Cruz".center(60) + "=========|")
     print("|=========" + " ".center(60) + "=========|")
     print("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
-    print("|=========" + "Oklahoma State University ECE Department".center(60) + "=========|")
+    print("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|")
+    print("|=========" + "Oklahoma State University".center(60) + "=========|")
     print("|=========" + " ".center(60) + "=========|")
     user_info = "Usage help: openram-user-group@ucsc.edu"
     print("|=========" + user_info.center(60) + "=========|")
@@ -223,13 +225,17 @@ def read_config(config_file, is_unit_test=True):
         
     # If config didn't set output name, make a reasonable default.
     if (OPTS.output_name == ""):
-        OPTS.output_name = "sram_{0}b_{1}w_{2}bank_{3}rw_{4}w_{5}r_{6}".format(OPTS.word_size,
-                                                                               OPTS.num_words,
-                                                                               OPTS.num_banks,
-                                                                               OPTS.num_rw_ports,
-                                                                               OPTS.num_w_ports,
-                                                                               OPTS.num_r_ports,
-                                                                               OPTS.tech_name)
+        ports = ""
+        if OPTS.num_rw_ports>0:
+            ports += "{}rw_".format(OPTS.num_rw_ports)
+        if OPTS.num_w_ports>0:
+            ports += "{}w_".format(OPTS.num_w_ports)
+        if OPTS.num_r_ports>0:
+            ports += "{}r_".format(OPTS.num_r_ports)
+        OPTS.output_name = "sram_{0}b_{1}_{2}{3}".format(OPTS.word_size,
+                                                         OPTS.num_words,
+                                                         ports,
+                                                         OPTS.tech_name)
         
 
         
@@ -387,8 +393,6 @@ def report_status():
         debug.error("{0} is not an integer in config file.".format(OPTS.word_size))
     if type(OPTS.num_words)!=int:
         debug.error("{0} is not an integer in config file.".format(OPTS.sram_size))
-    if type(OPTS.num_banks)!=int:
-        debug.error("{0} is not an integer in config file.".format(OPTS.num_banks))
 
     if not OPTS.tech_name:
         debug.error("Tech name must be specified in config file.")

compiler/options.py

@@ -64,9 +64,11 @@ class options(optparse.Values):
     # These are the main configuration parameters that should be over-ridden
     # in a configuration file.
     #num_words = 0
-    #num_banks = 1
     #word_size = 0
 
+    # You can manually specify banks, but it is better to auto-detect it.
+    num_banks = 1
+    
     # These are the default modules that can be over-riden
     decoder = "hierarchical_decoder"
     dff_array = "dff_array"

compiler/router/tests/config_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 1
 num_words = 16
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

compiler/router/tests/config_scn3me_subm.py

@@ -1,6 +1,5 @@
 word_size = 1
 num_words = 16
-num_banks = 1
 
 tech_name = "scn3me_subm"
 process_corners = ["TT"]

compiler/tests/config_20_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 1
 num_words = 16
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

compiler/tests/config_20_scn3me_subm.py

@@ -1,6 +1,5 @@
 word_size = 1
 num_words = 16
-num_banks = 1
 
 tech_name = "scn3me_subm"
 process_corners = ["TT"]

compiler/tests/config_20_scn4m_subm.py

@@ -1,6 +1,5 @@
 word_size = 1
 num_words = 16
-num_banks = 1
 
 tech_name = "scn4m_subm"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py

@@ -1,8 +0,0 @@
-word_size = 128
-num_words = 1024
-num_banks = 2
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]

lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py

@@ -1,8 +0,0 @@
-word_size = 128
-num_words = 1024
-num_banks = 4
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]

lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py

@@ -1,8 +0,0 @@
-word_size = 64
-num_words = 1024
-num_banks = 2
-
-tech_name = "freepdk45"
-process_corners = ["TT"]
-supply_voltages = [1.0]
-temperatures = [25]

lib/freepdk45/configs/sram_32b_1024_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 32
 num_words = 1024
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_32b_2048_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 32
 num_words = 2048
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_32b_256_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 32
 num_words = 256
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_32b_512_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 32
 num_words = 512
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_64b_1024_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 64
 num_words = 1024
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_8b_1024_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 8
 num_words = 1024
-num_banks = 4
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_8b_256_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 8
 num_words = 256
-num_banks = 1
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/configs/sram_8b_512_1rw_freepdk45.py

@@ -1,6 +1,5 @@
 word_size = 8
 num_words = 512
-num_banks = 4
 
 tech_name = "freepdk45"
 process_corners = ["TT"]

lib/freepdk45/lib/sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 128;
-    bit_from : 0;
-    bit_to : 127;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_128b_1024w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 128;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 146602.501987;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.56084648;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[127:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("3.107, 3.109, 3.117",\
-                   "3.109, 3.11, 3.118",\
-                   "3.114, 3.115, 3.123");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.27, 0.274, 0.297",\
-                   "0.271, 0.274, 0.298",\
-                   "0.277, 0.28, 0.303");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.023, 0.024, 0.034",\
-                   "0.023, 0.024, 0.034",\
-                   "0.023, 0.024, 0.034");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.055, 0.057, 0.077",\
-                   "0.055, 0.057, 0.077",\
-                   "0.055, 0.058, 0.077");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.359934198778");
-            }
-            fall_power(scalar){
-                values("0.359934198778");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.377816169333");
-            }
-            fall_power(scalar){
-                values("0.377816169333");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.969"); 
-            }
-            fall_constraint(scalar) {
-                values("2.969"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("5.938"); 
-            }
-            fall_constraint(scalar) {
-                values("5.938"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 128;
-    bit_from : 0;
-    bit_to : 127;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_128b_1024w_4bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 128;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 178744.321438;
-
-    leakage_power () {
-      when : "CSb";
-      value : 1.2037325;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[127:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.177, 0.178, 0.186",\
-                   "0.177, 0.178, 0.186",\
-                   "0.183, 0.184, 0.192");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.158, 0.159, 0.168",\
-                   "0.159, 0.16, 0.168",\
-                   "0.164, 0.165, 0.174");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.08, 0.081, 0.091",\
-                   "0.08, 0.081, 0.091",\
-                   "0.081, 0.082, 0.091");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.077, 0.079, 0.093",\
-                   "0.077, 0.079, 0.093",\
-                   "0.078, 0.079, 0.093");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.719680893333");
-            }
-            fall_power(scalar){
-                values("0.719680893333");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.767111023611");
-            }
-            fall_power(scalar){
-                values("0.767111023611");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.0155"); 
-            }
-            fall_constraint(scalar) {
-                values("1.0155"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.031"); 
-            }
-            fall_constraint(scalar) {
-                values("2.031"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_32b_1024w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 42051.1147875;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.15279765;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("1.158, 1.159, 1.167",\
-                   "1.158, 1.161, 1.167",\
-                   "1.164, 1.165, 1.171");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.171, 0.173, 0.186",\
-                   "0.172, 0.173, 0.186",\
-                   "0.177, 0.179, 0.192");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.02, 0.021, 0.032",\
-                   "0.02, 0.021, 0.032",\
-                   "0.02, 0.021, 0.031");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.065, 0.063, 0.058",\
-                   "0.065, 0.063, 0.058",\
-                   "0.066, 0.064, 0.058");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.177355641117");
-            }
-            fall_power(scalar){
-                values("0.177355641117");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.193822578894");
-            }
-            fall_power(scalar){
-                values("0.193822578894");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.094"); 
-            }
-            fall_constraint(scalar) {
-                values("1.094"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.188"); 
-            }
-            fall_constraint(scalar) {
-                values("2.188"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 11;
-    bit_from : 0;
-    bit_to : 10;
-    }
-
-cell (sram_1rw_32b_2048w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 11;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 116044.35785;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.306155;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("1.22, 1.223, 1.23",\
-                   "1.222, 1.221, 1.238",\
-                   "1.232, 1.234, 1.237");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.235, 0.237, 0.251",\
-                   "0.235, 0.237, 0.252",\
-                   "0.241, 0.243, 0.257");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.02, 0.021, 0.032",\
-                   "0.02, 0.022, 0.032",\
-                   "0.02, 0.022, 0.032");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.131, 0.13, 0.072",\
-                   "0.132, 0.13, 0.072",\
-                   "0.132, 0.131, 0.074");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[10:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.37352892");
-            }
-            fall_power(scalar){
-                values("0.37352892");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.392384140556");
-            }
-            fall_power(scalar){
-                values("0.392384140556");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.172"); 
-            }
-            fall_constraint(scalar) {
-                values("1.172"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.344"); 
-            }
-            fall_constraint(scalar) {
-                values("2.344"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 8;
-    bit_from : 0;
-    bit_to : 7;
-    }
-
-cell (sram_1rw_32b_256w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 8;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 12335.4213125;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.040298101;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("1.116, 1.117, 1.124",\
-                   "1.116, 1.117, 1.124",\
-                   "1.122, 1.123, 1.13");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.118, 0.119, 0.132",\
-                   "0.118, 0.12, 0.133",\
-                   "0.124, 0.125, 0.138");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.028, 0.03, 0.046",\
-                   "0.028, 0.03, 0.046",\
-                   "0.029, 0.03, 0.046");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[7:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.0644972321667");
-            }
-            fall_power(scalar){
-                values("0.0644972321667");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.0770882050833");
-            }
-            fall_power(scalar){
-                values("0.0770882050833");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.0545"); 
-            }
-            fall_constraint(scalar) {
-                values("1.0545"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.109"); 
-            }
-            fall_constraint(scalar) {
-                values("2.109"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 9;
-    bit_from : 0;
-    bit_to : 8;
-    }
-
-cell (sram_1rw_32b_512w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 9;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 22454.71095;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.077704284;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("1.128, 1.129, 1.136",\
-                   "1.128, 1.129, 1.136",\
-                   "1.134, 1.135, 1.142");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.136, 0.138, 0.15",\
-                   "0.137, 0.139, 0.151",\
-                   "0.142, 0.144, 0.157");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.034, 0.036, 0.05",\
-                   "0.035, 0.036, 0.05",\
-                   "0.035, 0.036, 0.05");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[8:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.0998806242278");
-            }
-            fall_power(scalar){
-                values("0.0998806242278");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.114319477006");
-            }
-            fall_power(scalar){
-                values("0.114319477006");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.094"); 
-            }
-            fall_constraint(scalar) {
-                values("1.094"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("2.188"); 
-            }
-            fall_constraint(scalar) {
-                values("2.188"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 64;
-    bit_from : 0;
-    bit_to : 63;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_64b_1024w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 64;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 76901.5771875;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.30184115;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[63:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("1.836, 1.837, 1.844",\
-                   "1.837, 1.838, 1.846",\
-                   "1.843, 1.843, 1.851");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.208, 0.211, 0.227",\
-                   "0.209, 0.211, 0.228",\
-                   "0.214, 0.217, 0.233");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.021, 0.022, 0.032",\
-                   "0.021, 0.022, 0.032",\
-                   "0.021, 0.022, 0.032");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.049, 0.05, 0.063",\
-                   "0.049, 0.05, 0.063",\
-                   "0.049, 0.05, 0.064");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.269265398756");
-            }
-            fall_power(scalar){
-                values("0.269265398756");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.293634058756");
-            }
-            fall_power(scalar){
-                values("0.293634058756");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.797"); 
-            }
-            fall_constraint(scalar) {
-                values("1.797"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("3.594"); 
-            }
-            fall_constraint(scalar) {
-                values("3.594"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/lib/sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 1.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 1.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.052275, 0.2091, 1.6728");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.00125, 0.005, 0.04");
-        index_2("0.00125, 0.005, 0.04");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 8;
-    bit_from : 0;
-    bit_to : 7;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 8;
-    bit_from : 0;
-    bit_to : 7;
-    }
-
-cell (sram_1rw_8b_256w_1bank_freepdk45){
-    memory(){ 
-    type : ram;
-    address_width : 8;
-    word_width : 8;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 4498.9233125;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.011168618;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 1.6728;  
-        min_capacitance : 0.052275;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[7:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("0.556, 0.557, 0.564",\
-                   "0.556, 0.557, 0.564",\
-                   "0.562, 0.563, 0.57");
-            }
-            cell_fall(CELL_TABLE) {
-            values("0.088, 0.089, 0.098",\
-                   "0.088, 0.09, 0.099",\
-                   "0.094, 0.095, 0.104");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031",\
-                   "0.02, 0.021, 0.031");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.03, 0.03, 0.041",\
-                   "0.031, 0.03, 0.041",\
-                   "0.031, 0.031, 0.041");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 0.2091;  
-        max_transition       : 0.04;
-        pin(ADDR[7:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 0.2091;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021",\
-                   "0.009, 0.015, 0.021");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015",\
-                   "0.009, 0.009, 0.015");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004",\
-                   "0.002, 0.002, -0.004");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016",\
-                   "-0.004, -0.004, -0.016");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 0.2091;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("0.0382237081278");
-            }
-            fall_power(scalar){
-                values("0.0382237081278");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("0.0443502652111");
-            }
-            fall_power(scalar){
-                values("0.0443502652111");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("0.5275"); 
-            }
-            fall_constraint(scalar) {
-                values("0.5275"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("1.055"); 
-            }
-            fall_constraint(scalar) {
-                values("1.055"); 
-            }
-         }
-    }
-    }
-}

lib/freepdk45/sram_1rw_128b_1024w_1bank_freepdk45.log

@@ -1,138 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_12899_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_12899_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_128b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 128
-Words: 1024
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 16:26:13.838687 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 52 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 15917	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 17508	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 21120	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 256 x 512
-[verify.calibre/run_drc]: bitcell_array	Geometries: 39847938	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 89090	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 48389	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 31747	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 41475	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_256rows	Geometries: 70385	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5877	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 75270	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 22788	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 70146	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 40382617	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_128b_1024w_1bank_freepdk45	Geometries: 40410068	Checks: 167	Errors: 0
-** SRAM creation: 3506.7 seconds
-SP: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.sp
-** Spice writing: 0.6 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_12899_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 1111111111 address
-[characterizer.trim_spice/trim]: Keeping 127 data bit
-[characterizer.trim_spice/trim]: Keeping bl[511] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 10.0ns feasible_delay 3.1226964ns/0.30308602ns slew 0.034041887ns/0.077321978ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 5.0ns (ub: 10.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 7.5ns (ub: 10.0 lb: 5.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 6.25ns (ub: 7.5 lb: 5.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 5.625ns (ub: 6.25 lb: 5.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 5.9375ns (ub: 6.25 lb: 5.625)
-[characterizer.delay/find_min_period]: MinPeriod Search: 5.78125ns (ub: 5.9375 lb: 5.625)
-[characterizer.delay/analyze]: Min Period: 5.9375n with a delay of 3.1226964 / 0.30308602
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 16788.8 seconds
-GDS: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.gds
-** GDS: 9.0 seconds
-LEF: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.lef
-** LEF: 24.4 seconds
-Verilog: Writing to ./sram_1rw_128b_1024w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 20330.3 seconds

lib/freepdk45/sram_1rw_128b_1024w_2bank_freepdk45.log

@@ -1,62 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18643_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_2bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_18643_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_128b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 128
-Words: 1024
-Banks: 2
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-23 19:17:15.047539 seconds
-[sram/compute_sizes]: Words per row: 2
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 52 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 15917	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 17508	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 21120	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 256 x 256
-[verify.calibre/run_drc]: bitcell_array	Geometries: 19924226	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 44546	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 24323	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 31747	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 41475	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_256rows	Geometries: 70385	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5290	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 75270	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 22788	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 70146	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 20381520	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msb_address
-[verify.calibre/run_drc]: msb_address	Geometries: 594	Checks: 167	Errors: 0
-ERROR: file calibre.py: line 131: sram_1rw_128b_1024w_2bank_freepdk45	Geometries: 40824902	Checks: 167	Errors: 1
-ERROR: file design.py: line 87: DRC failed for sram_1rw_128b_1024w_2bank_freepdk45

lib/freepdk45/sram_1rw_128b_1024w_4bank_freepdk45.log

@@ -1,139 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_5959_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_128b_1024w_4bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_5959_temp/            =========|
-|==============================================================================|
-Output files are sram_1rw_128b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 128
-Words: 1024
-Banks: 4
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-23 19:35:43.956230 seconds
-[sram/compute_sizes]: Words per row: 2
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 26 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 7961	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 9383	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 12956	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 128 x 256
-[verify.calibre/run_drc]: bitcell_array	Geometries: 9962498	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 44546	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 24323	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 31747	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 41475	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_128rows	Geometries: 65237	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 4703	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 75270	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 22788	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 35074	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 10340523	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msb_address
-[verify.calibre/run_drc]: msb_address	Geometries: 1181	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_128b_1024w_4bank_freepdk45	Geometries: 42826713	Checks: 167	Errors: 0
-** SRAM creation: 439.1 seconds
-SP: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.sp
-** Spice writing: 0.2 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_5959_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 1111111111 address
-[characterizer.trim_spice/trim]: Keeping 127 data bit
-[characterizer.trim_spice/trim]: Keeping bl[254] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.19175762ns/0.17403244ns slew 0.091382364ns/0.093018754ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.953125ns (ub: 2.03125 lb: 1.875)
-[characterizer.delay/analyze]: Min Period: 2.03125n with a delay of 0.19175762 / 0.17403244
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 35039.9 seconds
-GDS: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.gds
-** GDS: 5.3 seconds
-LEF: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.lef
-** LEF: 36.1 seconds
-Verilog: Writing to ./sram_1rw_128b_1024w_4bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 35521.6 seconds

lib/freepdk45/sram_1rw_32b_1024w_1bank_freepdk45.log

@@ -1,137 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_25677_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_1024w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_25677_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_32b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 32
-Words: 1024
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 07:05:54.597754 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 52 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 15917	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 17508	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 21120	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 256 x 128
-[verify.calibre/run_drc]: bitcell_array	Geometries: 9962370	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 22274	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 12101	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 7939	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 10371	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_256rows	Geometries: 70385	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5877	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 18822	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 5700	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 70146	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 10249561	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_32b_1024w_1bank_freepdk45	Geometries: 10275380	Checks: 167	Errors: 0
-** SRAM creation: 428.3 seconds
-SP: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.sp
-** Spice writing: 0.2 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_25677_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 1111111111 address
-[characterizer.trim_spice/trim]: Keeping 31 data bit
-[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1713644ns/0.19182711ns slew 0.03149035ns/0.058154194ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
-[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1713644 / 0.19182711
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 8034.5 seconds
-GDS: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.gds
-** GDS: 3.3 seconds
-LEF: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.lef
-** LEF: 10.1 seconds
-Verilog: Writing to ./sram_1rw_32b_1024w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 8477.4 seconds

lib/freepdk45/sram_1rw_32b_2048w_1bank_freepdk45.log

@@ -1,137 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17202_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_2048w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_17202_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_32b_2048w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 32
-Words: 2048
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 12:31:22.490074 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 103 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 31523	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 33446	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 37135	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 512 x 128
-[verify.calibre/run_drc]: bitcell_array	Geometries: 19924354	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 22274	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 12101	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 7939	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 10371	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_512rows	Geometries: 242084	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 6464	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 18822	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 5700	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 140290	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 20402203	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_32b_2048w_1bank_freepdk45	Geometries: 20447018	Checks: 167	Errors: 0
-** SRAM creation: 1092.7 seconds
-SP: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.sp
-** Spice writing: 0.4 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17202_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 11111111111 address
-[characterizer.trim_spice/trim]: Keeping 31 data bit
-[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[511] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.2374402ns/0.25744693ns slew 0.031680287ns/0.073574058ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.34375ns (ub: 2.5 lb: 2.1875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.265625ns (ub: 2.34375 lb: 2.1875)
-[characterizer.delay/analyze]: Min Period: 2.34375n with a delay of 1.2374402 / 0.25744693
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 12972.2 seconds
-GDS: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.gds
-** GDS: 5.6 seconds
-LEF: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.lef
-** LEF: 17.3 seconds
-Verilog: Writing to ./sram_1rw_32b_2048w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 14089.0 seconds

lib/freepdk45/sram_1rw_32b_256w_1bank_freepdk45.log

@@ -1,137 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_18997_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_256w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_18997_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_32b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 32
-Words: 256
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-23 17:53:13.665862 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 13 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 3983	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 5321	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 8875	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 64 x 128
-[verify.calibre/run_drc]: bitcell_array	Geometries: 2490882	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 22274	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 12101	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 7939	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 10371	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_64rows	Geometries: 34473	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 4703	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 18822	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 5700	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 17538	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 2641339	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_32b_256w_1bank_freepdk45	Geometries: 2653124	Checks: 167	Errors: 0
-** SRAM creation: 160.0 seconds
-SP: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.sp
-** Spice writing: 0.1 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_256w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_18997_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 11111111 address
-[characterizer.trim_spice/trim]: Keeping 31 data bit
-[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1300259ns/0.13801474ns slew 0.031264005ns/0.046135884ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
-[characterizer.delay/analyze]: Min Period: 2.109375n with a delay of 1.1300259 / 0.13801474
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 4457.6 seconds
-GDS: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.gds
-** GDS: 1.4 seconds
-LEF: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.lef
-** LEF: 3.6 seconds
-Verilog: Writing to ./sram_1rw_32b_256w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 4623.9 seconds

lib/freepdk45/sram_1rw_32b_512w_1bank_freepdk45.log

@@ -1,137 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3435_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_32b_512w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_3435_temp/            =========|
-|==============================================================================|
-Output files are sram_1rw_32b_512w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 32
-Words: 512
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 23:05:39.265001 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 26 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 7961	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 9383	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 12956	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 128 x 128
-[verify.calibre/run_drc]: bitcell_array	Geometries: 4981378	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 22274	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 12101	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 7939	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 10371	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_128rows	Geometries: 65237	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5290	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 18822	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 5700	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 35074	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 5189587	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_32b_512w_1bank_freepdk45	Geometries: 5206208	Checks: 167	Errors: 0
-** SRAM creation: 219.2 seconds
-SP: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.sp
-** Spice writing: 0.1 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_32b_512w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_3435_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 111111111 address
-[characterizer.trim_spice/trim]: Keeping 31 data bit
-[characterizer.trim_spice/trim]: Keeping bl[127] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.1419594ns/0.15656674ns slew 0.031336377ns/0.049918723ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.875ns (ub: 2.5 lb: 1.25)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.1875ns (ub: 2.5 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.03125ns (ub: 2.1875 lb: 1.875)
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.109375ns (ub: 2.1875 lb: 2.03125)
-[characterizer.delay/analyze]: Min Period: 2.1875n with a delay of 1.1419594 / 0.15656674
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 5101.6 seconds
-GDS: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.gds
-** GDS: 1.8 seconds
-LEF: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.lef
-** LEF: 5.1 seconds
-Verilog: Writing to ./sram_1rw_32b_512w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 5328.7 seconds

lib/freepdk45/sram_1rw_64b_1024w_1bank_freepdk45.log

@@ -1,136 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_31317_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_31317_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_64b_1024w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 64
-Words: 1024
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 09:27:13.909126 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 52 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 15917	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 17508	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 21120	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 256 x 256
-[verify.calibre/run_drc]: bitcell_array	Geometries: 19924226	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 44546	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 24197	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 15875	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 20739	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_256rows	Geometries: 70385	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5877	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 37638	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 11396	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 70146	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 20293913	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_64b_1024w_1bank_freepdk45	Geometries: 20320276	Checks: 167	Errors: 0
-** SRAM creation: 1075.6 seconds
-SP: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.sp
-** Spice writing: 0.3 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_31317_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 1111111111 address
-[characterizer.trim_spice/trim]: Keeping 63 data bit
-[characterizer.trim_spice/trim]: Keeping bl[255] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 1.850756ns/0.23319319ns slew 0.032157888ns/0.063655528ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 3.75ns (ub: 5.0 lb: 2.5)
-[characterizer.delay/find_min_period]: MinPeriod Search: 3.125ns (ub: 3.75 lb: 2.5)
-[characterizer.delay/find_min_period]: MinPeriod Search: 3.4375ns (ub: 3.75 lb: 3.125)
-[characterizer.delay/find_min_period]: MinPeriod Search: 3.59375ns (ub: 3.75 lb: 3.4375)
-[characterizer.delay/analyze]: Min Period: 3.59375n with a delay of 1.850756 / 0.23319319
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 9948.6 seconds
-GDS: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.gds
-** GDS: 5.9 seconds
-LEF: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.lef
-** LEF: 15.0 seconds
-Verilog: Writing to ./sram_1rw_64b_1024w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 11046.3 seconds

lib/freepdk45/sram_1rw_64b_1024w_2bank_freepdk45.log

@@ -1,62 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_3114_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_64b_1024w_2bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_3114_temp/            =========|
-|==============================================================================|
-Output files are sram_1rw_64b_1024w_2bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 64
-Words: 1024
-Banks: 2
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-23 19:10:19.014431 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 26 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 7961	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 9383	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 12956	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 128 x 256
-[verify.calibre/run_drc]: bitcell_array	Geometries: 9962498	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 44546	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 24197	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 15875	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 20739	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_128rows	Geometries: 65237	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 5290	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 37638	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 11396	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 35074	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 10255431	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msb_address
-[verify.calibre/run_drc]: msb_address	Geometries: 594	Checks: 167	Errors: 0
-ERROR: file calibre.py: line 131: sram_1rw_64b_1024w_2bank_freepdk45	Geometries: 20550242	Checks: 167	Errors: 1
-ERROR: file design.py: line 87: DRC failed for sram_1rw_64b_1024w_2bank_freepdk45

lib/freepdk45/sram_1rw_8b_1024w_1bank_freepdk45.log

@@ -1,86 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_16936_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_1024w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_16936_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_8b_1024w_4bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 8
-Words: 1024
-Banks: 4
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 22:05:07.033164 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 13 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 3983	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 5321	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 8875	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 64 x 32
-[verify.calibre/run_drc]: bitcell_array	Geometries: 622818	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 5570	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 3029	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 1987	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 2595	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_64rows	Geometries: 34473	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 4703	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 4710	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 1428	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 17538	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 713631	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msb_address
-[verify.calibre/run_drc]: msb_address	Geometries: 1181	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_8b_1024w_4bank_freepdk45	Geometries: 3116996	Checks: 167	Errors: 0
-** SRAM creation: 155.1 seconds
-SP: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45.sp
-** Spice writing: 0.0 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_1024w_4bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_16936_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 1111111111 address
-[characterizer.trim_spice/trim]: Keeping 7 data bit
-[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[255] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
-ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

lib/freepdk45/sram_1rw_8b_256w_1bank_freepdk45.log

@@ -1,138 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_17125_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_256w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_17125_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_8b_256w_1bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 8
-Words: 256
-Banks: 1
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 06:07:13.473469 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 13 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 3983	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 5321	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 8875	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 64 x 32
-[verify.calibre/run_drc]: bitcell_array	Geometries: 622818	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 5570	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 3029	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 1987	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 2595	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_64rows	Geometries: 34473	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 4703	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 4710	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 1428	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 17538	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 711403	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_8b_256w_1bank_freepdk45	Geometries: 722780	Checks: 167	Errors: 0
-** SRAM creation: 147.1 seconds
-SP: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.sp
-** Spice writing: 0.0 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_256w_1bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_17125_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 11111111 address
-[characterizer.trim_spice/trim]: Keeping 7 data bit
-[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[63] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Found feasible_period: 5.0ns feasible_delay 0.56986783ns/0.10418749ns slew 0.031200233ns/0.040857947ns
-[characterizer.delay/find_min_period]: MinPeriod Search: 2.5ns (ub: 5.0 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.25ns (ub: 2.5 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 0.625ns (ub: 1.25 lb: 0.0)
-[characterizer.delay/find_min_period]: MinPeriod Search: 0.9375ns (ub: 1.25 lb: 0.625)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.09375ns (ub: 1.25 lb: 0.9375)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.015625ns (ub: 1.09375 lb: 0.9375)
-[characterizer.delay/find_min_period]: MinPeriod Search: 1.0546875ns (ub: 1.09375 lb: 1.015625)
-[characterizer.delay/analyze]: Min Period: 1.0546875n with a delay of 0.56986783 / 0.10418749
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.00125 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.005 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.00125
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414063
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.005
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.0085449219
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: 0.0024414062
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.0036621094
-[characterizer.setup_hold/analyze]: Clock slew: 0.04 Data slew: 0.04
-[characterizer.setup_hold/analyze]:   Setup Time for low_to_high transition: 0.020751953
-[characterizer.setup_hold/analyze]:   Setup Time for high_to_low transition: 0.014648437
-[characterizer.setup_hold/analyze]:   Hold Time for low_to_high transition: -0.0036621094
-[characterizer.setup_hold/analyze]:   Hold Time for high_to_low transition: -0.015869141
-** Characterization: 3369.3 seconds
-GDS: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.gds
-** GDS: 0.8 seconds
-LEF: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.lef
-** LEF: 2.0 seconds
-Verilog: Writing to ./sram_1rw_8b_256w_1bank_freepdk45.v
-** Verilog: 0.0 seconds
-** End: 3520.0 seconds

lib/freepdk45/sram_1rw_8b_512w_1bank_freepdk45.log

@@ -1,86 +0,0 @@
-[globals/init_openram]: Initializing OpenRAM...
-[globals/setup_paths]: Temporary files saved in /tmp/openram_mrg_21736_temp/
-[globals/read_config]: Configuration file is /soe/mrg/OpenRAM/lib/freepdk45/configs/sram_1rw_8b_512w_1bank_freepdk45.py
-[globals/read_config]: Output saved in ./
-[globals/import_tech]: Technology path is /soe/mrg/OpenRAM/technology/freepdk45/
-|==============================================================================|
-|=========                      OpenRAM Compiler                      =========|
-|=========                                                            =========|
-|=========               VLSI Design and Automation Lab               =========|
-|=========     University of California Santa Cruz CE Department      =========|
-|=========                                                            =========|
-|=========         VLSI Computer Architecture Research Group          =========|
-|=========          Oklahoma State University ECE Department          =========|
-|=========                                                            =========|
-|=========          Usage help: openram-user-group@ucsc.edu           =========|
-|=========        Development help: openram-dev-group@ucsc.edu        =========|
-|=========           Temp dir: /tmp/openram_mrg_21736_temp/           =========|
-|==============================================================================|
-Output files are sram_1rw_8b_512w_4bank_freepdk45.(sp|gds|v|lib|lef)
-Technology: freepdk45
-Word size: 8
-Words: 512
-Banks: 4
-[globals/get_tool]: Using DRC: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using LVS: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-[globals/get_tool]: Using PEX: /bsoe/software/mentor/calibre/aoi_cal_2017.3_29.23/bin/calibre
-** Start: 2018-02-24 05:27:47.667578 seconds
-[sram/compute_sizes]: Words per row: 4
-[control_logic/__init__]: Creating control_logic
-[ms_flop_array/__init__]: Creating msf_control
-[verify.calibre/run_drc]: msf_control	Geometries: 1768	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitline_load 7 x 1
-[verify.calibre/run_drc]: bitline_load	Geometries: 2147	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: delay_chain	Geometries: 906	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: replica_bitline	Geometries: 3446	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: control_logic	Geometries: 6991	Checks: 167	Errors: 0
-[bitcell_array/__init__]: Creating bitcell_array 32 x 32
-[verify.calibre/run_drc]: bitcell_array	Geometries: 311458	Checks: 167	Errors: 0
-[precharge_array/__init__]: Creating precharge_array
-[verify.calibre/run_drc]: precharge	Geometries: 86	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: precharge_array	Geometries: 5570	Checks: 167	Errors: 0
-[single_level_column_mux_array/__init__]: Creating columnmux_array
-[verify.calibre/run_drc]: columnmux_array	Geometries: 3029	Checks: 167	Errors: 0
-[sense_amp_array/__init__]: Creating sense_amp_array
-[verify.calibre/run_drc]: sense_amp_array	Geometries: 1987	Checks: 167	Errors: 0
-[write_driver_array/__init__]: Creating write_driver_array
-[verify.calibre/run_drc]: write_driver_array	Geometries: 2595	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre2x4	Geometries: 969	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: pre3x8	Geometries: 2251	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: hierarchical_decoder_32rows	Geometries: 9834	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_address
-[verify.calibre/run_drc]: msf_address	Geometries: 4116	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msf_data_in
-[verify.calibre/run_drc]: msf_data_in	Geometries: 4710	Checks: 167	Errors: 0
-[tri_gate_array/__init__]: Creating tri_gate_array
-[verify.calibre/run_drc]: tri_gate_array	Geometries: 1428	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: wordline_driver	Geometries: 8770	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: bank	Geometries: 366234	Checks: 167	Errors: 0
-[ms_flop_array/__init__]: Creating msb_address
-[verify.calibre/run_drc]: msb_address	Geometries: 1181	Checks: 167	Errors: 0
-[verify.calibre/run_drc]: sram_1rw_8b_512w_4bank_freepdk45	Geometries: 1621777	Checks: 167	Errors: 0
-** SRAM creation: 151.4 seconds
-SP: Writing to ./sram_1rw_8b_512w_4bank_freepdk45.sp
-** Spice writing: 0.0 seconds
-[globals/get_tool]: Using spice: /bsoe/software/synopsys/xa/bin/xa
-LIB: Characterizing... 
-Performing simulation-based characterization with xa
-Trimming netlist to speed up characterization.
-[characterizer.lib/prepare_tables]: Loads: [ 0.052275  0.2091    1.6728  ]
-[characterizer.lib/prepare_tables]: Slews: [ 0.00125  0.005    0.04   ]
-[characterizer.lib/characterize_corners]: Corner: ('TT', 1.0, 25)
-[characterizer.lib/characterize_corners]: Writing to ./sram_1rw_8b_512w_4bank_freepdk45_TT_1p0V_25C.lib
-[characterizer.trim_spice/__init__]: Trimming non-critical cells to speed-up characterization: /tmp/openram_mrg_21736_temp/reduced.sp.
-[characterizer.trim_spice/trim]: Keeping 111111111 address
-[characterizer.trim_spice/trim]: Keeping 7 data bit
-[characterizer.trim_spice/trim]: Keeping bl[31] (trimming other BLs)
-[characterizer.trim_spice/trim]: Keeping wl[127] (trimming other WLs)
-[characterizer.delay/find_feasible_period]: Trying feasible period: 5.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 10.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 20.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 40.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 80.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 160.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 320.0ns
-[characterizer.delay/find_feasible_period]: Trying feasible period: 640.0ns
-ERROR: file delay.py: line 309: Timed out, could not find a feasible period.

lib/freepdk45/verilog/sram_1rw_128b_1024w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 1024
-// Word size: 128
-
-module sram_1rw_128b_1024w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 128 ;
-  parameter ADDR_WIDTH = 10 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 128'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_128b_1024w_4bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 1024
-// Word size: 128
-
-module sram_1rw_128b_1024w_4bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 128 ;
-  parameter ADDR_WIDTH = 10 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 128'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_32b_1024w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 1024
-// Word size: 32
-
-module sram_1rw_32b_1024w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 10 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_32b_2048w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 2048
-// Word size: 32
-
-module sram_1rw_32b_2048w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 11 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_32b_256w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 256
-// Word size: 32
-
-module sram_1rw_32b_256w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 8 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_32b_512w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 512
-// Word size: 32
-
-module sram_1rw_32b_512w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 9 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 32'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_64b_1024w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 1024
-// Word size: 64
-
-module sram_1rw_64b_1024w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 64 ;
-  parameter ADDR_WIDTH = 10 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 64'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/freepdk45/verilog/sram_1rw_8b_256w_1bank_freepdk45.v

@@ -1,47 +0,0 @@
-// OpenRAM SRAM model
-// Words: 256
-// Word size: 8
-
-module sram_1rw_8b_256w_1bank_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
-
-  parameter DATA_WIDTH = 8 ;
-  parameter ADDR_WIDTH = 8 ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  parameter DELAY = 3 ;
-
-  inout [DATA_WIDTH-1:0] DATA;
-  input [ADDR_WIDTH-1:0] ADDR;
-  input CSb;             // active low chip select
-  input WEb;             // active low write control
-  input OEb;             // active output enable
-  input clk;             // clock
-
-  reg [DATA_WIDTH-1:0] data_out ;
-  reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
-
-  // Tri-State Buffer control
-  // output : When WEb = 1, oeb = 0, csb = 0
-  assign DATA = (!CSb && !OEb && WEb) ? data_out : 8'bz;
-
-  // Memory Write Block
-  // Write Operation : When WEb = 0, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_WRITE
-  if ( !CSb && !WEb ) begin
-    mem[ADDR] = DATA;
-    $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
-    end
-  end
-
-
-  // Memory Read Block
-  // Read Operation : When WEb = 1, CSb = 0
-  always @ (posedge clk)
-  begin : MEM_READ
-  if (!CSb && WEb) begin
-    data_out <= #(DELAY) mem[ADDR];
-    $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
-    end
-  end
-
-endmodule

lib/scn3me_subm/configs/sram_1rw_128b_1024w_1bank_scn3me_subm.py

@@ -1,8 +0,0 @@
-word_size = 128
-num_words = 1024
-num_banks = 1
-
-tech_name = "scn3me_subm"
-process_corners = ["TT"]
-supply_voltages = [ 5.0 ]
-temperatures = [ 25 ]

lib/scn3me_subm/configs/sram_1rw_128b_1024w_4bank_scn3me_subm.py

@@ -1,8 +0,0 @@
-word_size = 128
-num_words = 1024
-num_banks = 4
-
-tech_name = "scn3me_subm"
-process_corners = ["TT"]
-supply_voltages = [ 5.0 ]
-temperatures = [ 25 ]

lib/scn3me_subm/configs/sram_1rw_64b_1024w_2bank_scn3me_subm.py

@@ -1,8 +0,0 @@
-word_size = 64
-num_words = 1024
-num_banks = 2
-
-tech_name = "scn3me_subm"
-process_corners = ["TT"]
-supply_voltages = [ 5.0 ]
-temperatures = [ 25 ]

lib/scn3me_subm/lib/sram_1rw_128b_1024w_1bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_128b_1024w_1bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 128;
-    bit_from : 0;
-    bit_to : 127;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_128b_1024w_1bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 128;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 21833106.12;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.10247282;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[127:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("31.136, 31.573, 31.783",\
-                   "31.138, 31.574, 31.785",\
-                   "31.181, 31.615, 31.822");
-            }
-            cell_fall(CELL_TABLE) {
-            values("2.529, 2.815, 3.924",\
-                   "2.532, 2.818, 3.928",\
-                   "2.572, 2.859, 3.966");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.368, 0.429, 1.161",\
-                   "0.369, 0.429, 1.162",\
-                   "0.369, 0.429, 1.161");
-            }
-            fall_transition(CELL_TABLE) {
-            values("1.381, 1.522, 2.126",\
-                   "1.381, 1.524, 2.127",\
-                   "1.383, 1.525, 2.131");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("5.37896885789");
-            }
-            fall_power(scalar){
-                values("5.37896885789");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("33.1108208246");
-            }
-            fall_power(scalar){
-                values("33.1108208246");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("30.0"); 
-            }
-            fall_constraint(scalar) {
-                values("30.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("60.0"); 
-            }
-            fall_constraint(scalar) {
-                values("60.0"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_128b_1024w_2bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_128b_1024w_2bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 128;
-    bit_from : 0;
-    bit_to : 127;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_128b_1024w_2bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 128;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 24881585.4;
-
-    leakage_power () {
-      when : "CSb";
-      value : 44.198587;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[127:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("9.206, 1.164, 9.606",\
-                   "9.207, 1.167, 9.618",\
-                   "9.249, 1.208, 9.657");
-            }
-            cell_fall(CELL_TABLE) {
-            values("1.259, 1.338, 1.963",\
-                   "1.262, 1.342, 1.966",\
-                   "1.303, 1.383, 2.006");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.456, 0.683, 1.298",\
-                   "0.456, 0.684, 1.298",\
-                   "0.456, 0.684, 1.297");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.709, 0.804, 1.888",\
-                   "0.709, 0.804, 1.889",\
-                   "0.709, 0.804, 1.889");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("52.3376104111");
-            }
-            fall_power(scalar){
-                values("52.3376104111");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("53.8071773833");
-            }
-            fall_power(scalar){
-                values("53.8071773833");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("8.75"); 
-            }
-            fall_constraint(scalar) {
-                values("8.75"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("17.5"); 
-            }
-            fall_constraint(scalar) {
-                values("17.5"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_128b_1024w_4bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_128b_1024w_4bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 128;
-    bit_from : 0;
-    bit_to : 127;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_128b_1024w_4bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 128;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 27236928.375;
-
-    leakage_power () {
-      when : "CSb";
-      value : 126.82311;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[127:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("10.069, 10.112, 10.48",\
-                   "10.073, 10.113, 10.484",\
-                   "10.115, 10.155, 10.526");
-            }
-            cell_fall(CELL_TABLE) {
-            values("1.584, 1.651, 2.289",\
-                   "1.587, 1.655, 2.292",\
-                   "1.628, 1.695, 2.331");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.746, 0.821, 11.821",\
-                   "0.746, 0.822, 11.823",\
-                   "0.745, 0.821, 11.807");
-            }
-            fall_transition(CELL_TABLE) {
-            values("1.108, 1.228, 2.31",\
-                   "1.108, 1.229, 2.31",\
-                   "1.109, 1.229, 2.31");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("74.6529198333");
-            }
-            fall_power(scalar){
-                values("74.6529198333");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("76.4449811944");
-            }
-            fall_power(scalar){
-                values("76.4449811944");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("9.375"); 
-            }
-            fall_constraint(scalar) {
-                values("9.375"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("18.75"); 
-            }
-            fall_constraint(scalar) {
-                values("18.75"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_32b_2048w_1bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_2048w_1bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 11;
-    bit_from : 0;
-    bit_to : 10;
-    }
-
-cell (sram_1rw_32b_2048w_1bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 11;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 12696470.64;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.50275213;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("8.762, 8.795, 9.18",\
-                   "8.755, 8.814, 9.174",\
-                   "8.798, 8.845, 9.2");
-            }
-            cell_fall(CELL_TABLE) {
-            values("2.037, 2.252, 3.065",\
-                   "2.041, 2.254, 3.068",\
-                   "2.08, 2.293, 3.105");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.335, 0.391, 1.153",\
-                   "0.335, 0.391, 1.155",\
-                   "0.335, 0.391, 1.153");
-            }
-            fall_transition(CELL_TABLE) {
-            values("1.591, 1.753, 1.713",\
-                   "1.591, 1.755, 1.714",\
-                   "1.591, 1.758, 1.719");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[10:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("28.9842694349");
-            }
-            fall_power(scalar){
-                values("28.9842694349");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("37.7906127405");
-            }
-            fall_power(scalar){
-                values("37.7906127405");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("8.4375"); 
-            }
-            fall_constraint(scalar) {
-                values("8.4375"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("16.875"); 
-            }
-            fall_constraint(scalar) {
-                values("16.875"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_32b_256w_1bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_256w_1bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 8;
-    bit_from : 0;
-    bit_to : 7;
-    }
-
-cell (sram_1rw_32b_256w_1bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 8;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 1840896.72;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.031524804;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("10.304, 10.336, 10.749",\
-                   "10.308, 10.34, 10.754",\
-                   "10.349, 10.381, 10.777");
-            }
-            cell_fall(CELL_TABLE) {
-            values("1.074, 1.21, 1.903",\
-                   "1.077, 1.213, 1.906",\
-                   "1.117, 1.253, 1.943");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.317, 0.659, 11.126",\
-                   "0.318, 0.658, 11.128",\
-                   "0.306, 0.677, 11.093");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.531, 0.608, 1.602",\
-                   "0.532, 0.611, 1.602",\
-                   "0.533, 0.617, 1.605");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[7:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("4.29313574236");
-            }
-            fall_power(scalar){
-                values("4.29313574236");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("12.810443259");
-            }
-            fall_power(scalar){
-                values("12.810443259");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("10.0"); 
-            }
-            fall_constraint(scalar) {
-                values("10.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("20.0"); 
-            }
-            fall_constraint(scalar) {
-                values("20.0"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_32b_512w_1bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_32b_512w_1bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 32;
-    bit_from : 0;
-    bit_to : 31;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 9;
-    bit_from : 0;
-    bit_to : 8;
-    }
-
-cell (sram_1rw_32b_512w_1bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 9;
-    word_width : 32;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 3322156.68;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.065826384;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[31:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("10.494, 10.458, 11.082",\
-                   "10.497, 10.462, 11.093",\
-                   "10.538, 10.502, 11.058");
-            }
-            cell_fall(CELL_TABLE) {
-            values("1.233, 1.383, 2.094",\
-                   "1.236, 1.386, 2.097",\
-                   "1.276, 1.426, 2.134");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.528, 0.608, 11.186",\
-                   "0.527, 0.607, 11.189",\
-                   "0.542, 0.618, 11.154");
-            }
-            fall_transition(CELL_TABLE) {
-            values("0.721, 0.834, 1.605",\
-                   "0.721, 0.836, 1.606",\
-                   "0.722, 0.84, 1.609");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[8:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("6.13928051527");
-            }
-            fall_power(scalar){
-                values("6.13928051527");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("15.3032656736");
-            }
-            fall_power(scalar){
-                values("15.3032656736");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("10.0"); 
-            }
-            fall_constraint(scalar) {
-                values("10.0"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("20.0"); 
-            }
-            fall_constraint(scalar) {
-                values("20.0"); 
-            }
-         }
-    }
-    }
-}

lib/scn3me_subm/lib/sram_1rw_64b_1024w_1bank_scn3me_subm_TT_5p0V_25C.lib

@@ -1,347 +0,0 @@
-library (sram_1rw_64b_1024w_1bank_scn3me_subm_TT_5p0V_25C_lib){
-    delay_model : "table_lookup";
-    time_unit : "1ns" ;
-    voltage_unit : "1v" ;
-    current_unit : "1mA" ;
-    resistance_unit : "1kohm" ;
-    capacitive_load_unit(1 ,fF) ;
-    leakage_power_unit : "1mW" ;
-    pulling_resistance_unit :"1kohm" ;
-    operating_conditions(OC){
-    process : 1.0 ;
-    voltage : 5.0 ;
-    temperature : 25;
-    }
-
-    input_threshold_pct_fall       :  50.0 ;
-    output_threshold_pct_fall      :  50.0 ;
-    input_threshold_pct_rise       :  50.0 ;
-    output_threshold_pct_rise      :  50.0 ;
-    slew_lower_threshold_pct_fall  :  10.0 ;
-    slew_upper_threshold_pct_fall  :  90.0 ;
-    slew_lower_threshold_pct_rise  :  10.0 ;
-    slew_upper_threshold_pct_rise  :  90.0 ;
-
-    nom_voltage : 5.0;
-    nom_temperature : 25;
-    nom_process : 1.0;
-    default_cell_leakage_power    : 0.0 ;
-    default_leakage_power_density : 0.0 ;
-    default_input_pin_cap    : 1.0 ;
-    default_inout_pin_cap    : 1.0 ;
-    default_output_pin_cap   : 0.0 ;
-    default_max_transition   : 0.5 ;
-    default_fanout_load      : 1.0 ;
-    default_max_fanout   : 4.0 ;
-    default_connection_class : universal ;
-
-    lu_table_template(CELL_TABLE){
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("2.45605, 9.8242, 78.5936");
-    }
-
-    lu_table_template(CONSTRAINT_TABLE){
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1("0.0125, 0.05, 0.4");
-        index_2("0.0125, 0.05, 0.4");
-    }
-
-    default_operating_conditions : OC; 
-
-
-    type (DATA){
-    base_type : array;
-    data_type : bit;
-    bit_width : 64;
-    bit_from : 0;
-    bit_to : 63;
-    }
-
-    type (ADDR){
-    base_type : array;
-    data_type : bit;
-    bit_width : 10;
-    bit_from : 0;
-    bit_to : 9;
-    }
-
-cell (sram_1rw_64b_1024w_1bank_scn3me_subm){
-    memory(){ 
-    type : ram;
-    address_width : 10;
-    word_width : 64;
-    }
-    interface_timing : true;
-    dont_use  : true;
-    map_only   : true;
-    dont_touch : true;
-    area : 11395617.48;
-
-    leakage_power () {
-      when : "CSb";
-      value : 0.10372818;
-    }
-    cell_leakage_power : 0;
-    bus(DATA){
-        bus_type  : DATA; 
-        direction  : inout; 
-        max_capacitance : 78.5936;  
-        min_capacitance : 2.45605;  
-        three_state : "!OEb & !clk"; 
-        memory_write(){ 
-            address : ADDR; 
-            clocked_on  : clk; 
-        }
-        memory_read(){ 
-            address : ADDR; 
-        }
-        pin(DATA[63:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        timing(){ 
-            timing_sense : non_unate; 
-            related_pin : "clk"; 
-            timing_type : falling_edge; 
-            cell_rise(CELL_TABLE) {
-            values("17.683, 17.574, 18.056",\
-                   "17.685, 17.577, 18.06",\
-                   "17.733, 17.618, 18.1");
-            }
-            cell_fall(CELL_TABLE) {
-            values("1.888, 2.11, 2.981",\
-                   "1.892, 2.113, 2.984",\
-                   "1.931, 2.153, 3.022");
-            }
-            rise_transition(CELL_TABLE) {
-            values("0.35, 0.41, 1.153",\
-                   "0.35, 0.411, 1.152",\
-                   "0.35, 0.411, 1.152");
-            }
-            fall_transition(CELL_TABLE) {
-            values("1.197, 1.33, 1.793",\
-                   "1.197, 1.332, 1.794",\
-                   "1.199, 1.334, 1.799");
-            }
-        }
-        }
-    }
-
-    bus(ADDR){
-        bus_type  : ADDR; 
-        direction  : input; 
-        capacitance : 9.8242;  
-        max_transition       : 0.4;
-        pin(ADDR[9:0]){
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-        }
-    }
-
-    pin(CSb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(OEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(WEb){
-        direction  : input; 
-        capacitance : 9.8242;  
-        timing(){ 
-            timing_type : setup_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149",\
-                   "0.076, 0.076, 0.149");
-            }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027",\
-                   "0.039, 0.039, 0.027");
-            }
-        }
-        timing(){ 
-            timing_type : hold_rising; 
-            related_pin  : "clk"; 
-            rise_constraint(CONSTRAINT_TABLE) {
-            values("-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009",\
-                   "-0.004, -0.004, 0.009");
-              }
-            fall_constraint(CONSTRAINT_TABLE) {
-            values("-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132",\
-                   "-0.052, -0.059, -0.132");
-            }
-        }
-    }
-
-    pin(clk){
-        clock             : true;
-        direction  : input; 
-        capacitance : 9.8242;  
-        internal_power(){
-            when : "!CSb & clk & !WEb"; 
-            rise_power(scalar){
-                values("7.00649382984");
-            }
-            fall_power(scalar){
-                values("7.00649382984");
-            }
-        }
-        internal_power(){
-            when : "!CSb & !clk & WEb"; 
-            rise_power(scalar){
-                values("22.1313182465");
-            }
-            fall_power(scalar){
-                values("22.1313182465");
-            }
-        }
-        internal_power(){
-            when : "CSb"; 
-            rise_power(scalar){
-                values("0");
-            }
-            fall_power(scalar){
-                values("0");
-            }
-        }
-        timing(){ 
-            timing_type :"min_pulse_width"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("16.875"); 
-            }
-            fall_constraint(scalar) {
-                values("16.875"); 
-            }
-         }
-        timing(){ 
-            timing_type :"minimum_period"; 
-            related_pin  : clk; 
-            rise_constraint(scalar) {
-                values("33.75"); 
-            }
-            fall_constraint(scalar) {
-                values("33.75"); 
-            }
-         }
-    }
-    }
-}