mirror of https://github.com/VLSIDA/OpenRAM.git
Changed part (4) of analyze to use the updated measure names.
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@ -415,7 +415,7 @@ class delay():
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power_names = ["read0_power_{0}".format(port), "write0_power_{0}".format(port),
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"read1_power_{0}".format(port), "write1_power_{0}".format(port)]
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powers = self.parse_values(delay_names, 1e3) # scale power to mw
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powers = self.parse_values(power_names, 1e3) # scale power to mw
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debug.check(len(powers) > 0,"Found valid delays but measured powers invalid.")
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result.update(powers)
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@ -642,15 +642,21 @@ class delay():
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char_data["min_period"] = round_time(min_period)
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# Make a list for each type of measurement to append results to
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for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
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"read1_power", "write0_power", "write1_power", "leakage_power"]:
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char_data[m]=[]
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for port in self.readwrite_ports+self.read_ports+self.write_ports:
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for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
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"read1_power", "write0_power", "write1_power", "leakage_power"]:
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char_data["{0}_{1}".format(m,port)]=[]
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# 3) Find the leakage power of the trimmmed and UNtrimmed arrays.
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(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
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char_data["leakage_power"]=full_array_leakage
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# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
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#Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
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self.targ_readwrite_ports = self.readwrite_ports
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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for slew in slews:
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for load in loads:
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self.set_load_slew(load,slew)
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