Altering multiport checks across several unit tests.

compiler/tests/16_control_logic_test.py

@@ -18,9 +18,22 @@ class control_logic_test(openram_test):
         import control_logic
         import tech
 
+        # check control logic for single port
         debug.info(1, "Testing sample for control_logic")
         a = control_logic.control_logic(num_rows=128)
         self.local_check(a)
+        
+        # check control logic for multi-port
+        # only layout for 1RW is supported at the moment
+        OPTS.bitcell = "pbitcell"
+        OPTS.replica_bitcell = "replica_pbitcell"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Testing sample for control_logic for multiport")
+        a = control_logic.control_logic(num_rows=128)
+        self.local_check(a)
 
         globals.end_openram()
         

compiler/tests/19_psingle_bank_test.py

@@ -52,18 +52,14 @@ class psingle_bank_test(openram_test):
         a = bank(c, name="bank1_1rw_0w_0r_single")
         self.local_check(a)
         
+        
+        # testing bank using pbitcell in various port combinations
+        # layout for multiple ports does not work yet
         """
-        # multiport can't generate layout yet on the bank level
         OPTS.netlist_only = True
-        
-        OPTS.num_rw_ports = 1
-        OPTS.num_w_ports = 1
-        OPTS.num_r_ports = 1
-        
-        debug.info(1, "No column mux")
-        name = "bank1_{0}rw_{1}w_{2}r_single".format(c.num_rw_ports, c.num_w_ports, c.num_r_ports)
-        a = bank(c, name=name)
-        self.local_check(a)
+
+        c.num_words=16
+        c.words_per_row=1
         
         OPTS.num_rw_ports = c.num_rw_ports = 2
         OPTS.num_w_ports = c.num_w_ports = 2
@@ -139,7 +135,7 @@ class psingle_bank_test(openram_test):
         self.local_check(a)
         """
         
-        #globals.end_openram()
+        globals.end_openram()
         
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":

compiler/tests/20_psram_1bank_test.py

@@ -19,8 +19,9 @@ class sram_1bank_test(openram_test):
         from sram import sram
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
+        OPTS.replica_bitcell="replica_pbitcell"
         
-        # testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
+        # testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
         OPTS.num_r_ports = 0
@@ -33,17 +34,79 @@ class sram_1bank_test(openram_test):
         debug.info(1, "Single bank, no column mux with control logic")
         a = sram(c, "sram1")
         self.local_check(a, final_verification=True)
+       
+        c.num_words=32
+        c.words_per_row=2
+        debug.info(1, "Single bank two way column mux with control logic")
+        a = sram(c, "sram2")
+        self.local_check(a, final_verification=True)
+
+        c.num_words=64
+        c.words_per_row=4
+        debug.info(1, "Single bank, four way column mux with control logic")
+        a = sram(c, "sram3")
+        self.local_check(a, final_verification=True)
+
+        c.word_size=2
+        c.num_words=128
+        c.words_per_row=8
+        debug.info(1, "Single bank, eight way column mux with control logic")
+        a = sram(c, "sram4")
+        self.local_check(a, final_verification=True)
         
+        # testing sram using pbitcell in various port combinations
+        # layout for multiple ports does not work yet
         """
-        OPTS.rw_ports = 1
-        OPTS.w_ports = 1
-        OPTS.r_ports = 1
         OPTS.netlist_only = True
         
+        c.num_words=16
+        c.words_per_row=1
+        
+        OPTS.num_rw_ports = 2
+        OPTS.num_w_ports = 2
+        OPTS.num_r_ports = 2
+        
         debug.info(1, "Single bank, no column mux with control logic")
         a = sram(c, "sram1")
         self.local_check(a, final_verification=True)
         
+        OPTS.num_rw_ports = 0
+        OPTS.num_w_ports = 2
+        OPTS.num_r_ports = 2
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        OPTS.num_rw_ports = 2
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 2
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        OPTS.num_rw_ports = 2
+        OPTS.num_w_ports = 2
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        OPTS.num_rw_ports = 2
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 0
+        
+        debug.info(1, "Single bank, no column mux with control logic")
+        a = sram(c, "sram1")
+        self.local_check(a, final_verification=True)
+        
+        # testing with various column muxes
+        OPTS.num_rw_ports = c.num_rw_ports = 2
+        OPTS.num_w_ports = c.num_w_ports = 2
+        OPTS.num_r_ports = c.num_r_ports = 2
+
         c.num_words=32
         c.words_per_row=2
         debug.info(1, "Single bank two way column mux with control logic")
@@ -63,7 +126,7 @@ class sram_1bank_test(openram_test):
         a = sram(c, "sram4")
         self.local_check(a, final_verification=True)
         """
-        #globals.end_openram()
+        globals.end_openram()
         
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":