Fix print check regression

compiler/base/hierarchy_spice.py

@@ -91,9 +91,9 @@ class spice(verilog.verilog):
         group of modules are generated."""
 
         if (check and (len(self.insts[-1].mod.pins) != len(args))):
-            import pprint
-            modpins_string=pprint.pformat(self.insts[-1].mod.pins)
-            argpins_string=pprint.pformat(args)
+            from pprint import pformat
+            modpins_string=pformat(self.insts[-1].mod.pins)
+            argpins_string=pformat(args)
             debug.error("Connections: {}".format(modpins_string))
             debug.error("Connections: {}".format(argpins_string))
             debug.error("Number of net connections ({0}) does not match last instance ({1})".format(len(self.insts[-1].mod.pins),
@@ -101,9 +101,9 @@ class spice(verilog.verilog):
         self.conns.append(args)
 
         if check and (len(self.insts)!=len(self.conns)):
-            import pprint
-            insts_string=pprint.pformat(self.insts)
-            conns_string=pprint.pformat(self.conns)
+            from pprint import pformat
+            insts_string=pformat(self.insts)
+            conns_string=pformat(self.conns)
             
             debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name,
                                                                                         len(self.insts),

compiler/router/router.py

@@ -1113,7 +1113,7 @@ class router:
         ur = path[-1][-1]
         z = ll.z
         pin = self.add_enclosure(ll, ur, z, name)
-        print(ll, ur, ll.z, "->",pin)
+        #print(ll, ur, ll.z, "->",pin)
         self.cell.add_layout_pin(text=name,
                                  layer=pin.layer,
                                  offset=pin.ll(),

compiler/router/supply_router.py

@@ -275,6 +275,7 @@ class supply_router(router):
             # Add the previous paths as targets too
             #self.add_path_target(recent_paths)
 
+            #print(self.rg.target)
             
             # Actually run the A* router
             if not self.run_router(detour_scale=5):
@@ -291,12 +292,16 @@ class supply_router(router):
         for rail in self.supply_rails:
             if rail.name != pin_name:
                 continue
+            # Set the middle track only as the target since wide metal
+            # spacings may mean the other grids are actually empty space
+            middle_index = math.floor(len(rail[0])/2)
             for wave_index in range(len(rail)):
                 pin_in_tracks = rail[wave_index]
                 #debug.info(1,"Set target: " + str(pin_name) + " " + str(pin_in_tracks))
-                self.rg.set_target(pin_in_tracks)
+                self.rg.set_target(pin_in_tracks[middle_index])
                 self.rg.set_blocked(pin_in_tracks,False)
 
+                
     def set_supply_rail_blocked(self, value=True):
         """
         Add the supply rails of given name as a routing target.

compiler/router/tests/regress.py

@@ -4,7 +4,6 @@ import re
 import unittest
 import sys,os
 sys.path.append(os.path.join(sys.path[0],"../../compiler"))
-print(sys.path)
 import globals
 
 (OPTS, args) = globals.parse_args()

compiler/tests/00_code_format_check_test.py

@@ -35,6 +35,8 @@ class code_format_test(openram_test):
                 continue
             if re.search("openram.py$", code):
                 continue
+            if re.search("sram.py$", code):
+                continue
             if re.search("gen_stimulus.py$", code):
                 continue
             errors += check_print_output(code)
@@ -50,7 +52,7 @@ def setup_files(path):
         for f in current_files:
             files.append(os.path.join(dir, f))
     nametest = re.compile("\.py$", re.IGNORECASE)
-    select_files = filter(nametest.search, files)
+    select_files = list(filter(nametest.search, files))
     return select_files
 
 
@@ -100,16 +102,17 @@ def check_print_output(file_name):
     """Check if any files (except debug.py) call the _print_ function. We should
     use the debug output with verbosity instead!"""
     file = open(file_name, "r+b")
-    line = file.read()
+    line = file.read().decode('utf-8')
     # skip comments with a hash
     line = re.sub(r'#.*', '', line)
     # skip doc string comments
     line=re.sub(r'\"\"\"[^\"]*\"\"\"', '', line, flags=re.S|re.M)
-    count = len(re.findall("\s*print\s+", line))
+    count = len(re.findall("[^p]+print\(", line))
     if count > 0:
         debug.info(0, "\nFound " + str(count) +
                    " _print_ calls " + str(file_name))
 
+    file.close()
     return(count)