Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.

This commit is contained in:
Michael Timothy Grimes 2018-09-12 01:53:41 -07:00
parent 7dfd37f79c
commit 42719b8ec2
3 changed files with 17 additions and 11 deletions

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@ -70,7 +70,10 @@ class pbitcell(design.design):
self.route_read_access()
self.extend_well()
self.offset_all_coordinates()
# in netlist_only mode, calling offset_all_coordinates will not be possible
# this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though
if not OPTS.netlist_only:
self.offset_all_coordinates()
self.DRC_LVS()
def add_pins(self):

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@ -41,8 +41,9 @@ class ptx(design.design):
self.num_contacts = num_contacts
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
# We must always create ptx layout for pbitcell
# some transistor sizes in other netlist depend on pbitcell
self.create_layout()

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@ -29,17 +29,19 @@ class openram_test(unittest.TestCase):
tempgds = OPTS.openram_temp + "temp.gds"
a.sp_write(tempspice)
a.gds_write(tempgds)
# cannot write gds in netlist_only mode
if not OPTS.netlist_only:
a.gds_write(tempgds)
import verify
result=verify.run_drc(a.name, tempgds)
if result != 0:
self.fail("DRC failed: {}".format(a.name))
import verify
result=verify.run_drc(a.name, tempgds)
if result != 0:
self.fail("DRC failed: {}".format(a.name))
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
if result != 0:
self.fail("LVS mismatch: {}".format(a.name))
result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
if result != 0:
self.fail("LVS mismatch: {}".format(a.name))
if OPTS.purge_temp:
self.cleanup()