mirror of https://github.com/VLSIDA/OpenRAM.git
Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.
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@ -70,7 +70,10 @@ class pbitcell(design.design):
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self.route_read_access()
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self.extend_well()
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self.offset_all_coordinates()
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# in netlist_only mode, calling offset_all_coordinates will not be possible
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# this function is not needed to calculate the dimensions of pbitcell in netlist_only mode though
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if not OPTS.netlist_only:
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self.offset_all_coordinates()
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self.DRC_LVS()
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def add_pins(self):
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@ -41,8 +41,9 @@ class ptx(design.design):
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self.num_contacts = num_contacts
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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# We must always create ptx layout for pbitcell
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# some transistor sizes in other netlist depend on pbitcell
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self.create_layout()
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@ -29,17 +29,19 @@ class openram_test(unittest.TestCase):
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tempgds = OPTS.openram_temp + "temp.gds"
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a.sp_write(tempspice)
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a.gds_write(tempgds)
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# cannot write gds in netlist_only mode
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if not OPTS.netlist_only:
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a.gds_write(tempgds)
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import verify
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result=verify.run_drc(a.name, tempgds)
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if result != 0:
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self.fail("DRC failed: {}".format(a.name))
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import verify
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result=verify.run_drc(a.name, tempgds)
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if result != 0:
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self.fail("DRC failed: {}".format(a.name))
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result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
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if result != 0:
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self.fail("LVS mismatch: {}".format(a.name))
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result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
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if result != 0:
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self.fail("LVS mismatch: {}".format(a.name))
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if OPTS.purge_temp:
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self.cleanup()
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