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Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

This commit is contained in:
Michael Timothy Grimes 2018-09-03 17:31:12 -07:00
parent f3cca7eea0
commit d3441c7ba4
4 changed files with 35 additions and 14 deletions
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20
compiler/modules/wordline_driver.py
View File

@ -58,6 +58,12 @@ class wordline_driver(design.design):
self.nand2 = pnand2()
self.add_mod(self.nand2)
from importlib import reload
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell = self.mod_bitcell()
self.add_mod(self.bitcell)
def route_vdd_gnd(self):
""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
@ -125,16 +131,20 @@ class wordline_driver(design.design):
nand2_xoffset = inv1_xoffset + self.inv.width
inv2_xoffset = nand2_xoffset + self.nand2.width
self.width = inv2_xoffset + self.inv.width
self.height = self.inv.height * self.rows
self.width = inv2_xoffset + self.inv.height
if self.bitcell.height > self.inv.height:
self.height = self.bitcell.height * self.rows
driver_height = self.bitcell.height
else:
self.height = self.inv.height * self.rows
driver_height = self.inv.height
for row in range(self.rows):
if (row % 2):
y_offset = self.inv.height*(row + 1)
y_offset = driver_height*(row + 1)
inst_mirror = "MX"
else:
y_offset = self.inv.height*row
y_offset = driver_height*row
inst_mirror = "R0"
inv1_offset = [inv1_xoffset, y_offset]

11
compiler/tests/08_wordline_driver_test.py Executable file → Normal file
View File

@ -20,10 +20,21 @@ class wordline_driver_test(openram_test):
import wordline_driver
import tech
# check wordline driver array in single port
debug.info(2, "Checking driver")
tx = wordline_driver.wordline_driver(rows=8)
self.local_check(tx)
# check wordline driver array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 1
OPTS.w_ports = 0
OPTS.r_ports = 0
debug.info(2, "Checking driver (multi-port case)")
tx = wordline_driver.wordline_driver(rows=8)
self.local_check(tx)
globals.end_openram()
# instantiate a copy of the class to actually run the test

8
compiler/tests/09_sense_amp_array_test.py
View File

@ -29,14 +29,14 @@ class sense_amp_test(openram_test):
# check sense amp array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 1
OPTS.w_ports = 1
OPTS.r_ports = 1
OPTS.w_ports = 0
OPTS.r_ports = 0
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
self.local_check(a)

10
compiler/tests/10_write_driver_array_test.py
View File

@ -29,18 +29,18 @@ class write_driver_test(openram_test):
# check write driver array in multi-port
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 1
OPTS.w_ports = 1
OPTS.r_ports = 1
OPTS.w_ports = 0
OPTS.r_ports = 0
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(columns=16, word_size=8)
self.local_check(a)
#globals.end_openram()
globals.end_openram()
# instantiate a copy of the class to actually run the test
if __name__ == "__main__":