mirror of https://github.com/VLSIDA/OpenRAM.git
Change tx mux size back to 8. Document why it was chosen.
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@ -10,20 +10,20 @@ class single_level_column_mux(design.design):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single columnmux cell with the given integer size relative
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to minimum size. Default is 2x.
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to minimum size. Default is 8x. Per Samira and Hodges-Jackson book:
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Column-mux transistors driven by the decoder must be sized for optimal speed
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"""
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# This is needed for different bitline spacings
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unique_id = 1
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def __init__(self, tx_size=2, bitcell_bl="bl", bitcell_br="br"):
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def __init__(self, tx_size=8, bitcell_bl="bl", bitcell_br="br"):
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self.tx_size = int(tx_size)
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name="single_level_column_mux_{}_{}".format(self.tx_size,single_level_column_mux.unique_id)
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single_level_column_mux.unique_id += 1
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design.design.__init__(self, name)
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debug.info(2, "create single column mux cell: {0}".format(name))
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self.tx_size = tx_size
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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