mirror of https://github.com/VLSIDA/OpenRAM.git
Adding functional test to characterizer and unit tests in both single and multiport
This commit is contained in:
Michael Timothy Grimes
parent
fc5f163828
commit
938ded3dd6
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@ -5,6 +5,7 @@ from globals import OPTS,find_exe,get_tool
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from .lib import *
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from .delay import *
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from .setup_hold import *
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from .functional import *
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debug.info(1,"Initializing characterizer...")
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@ -0,0 +1,320 @@
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import sys,re,shutil
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import debug
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import math
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import tech
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import random
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from .stimuli import *
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from .trim_spice import *
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from .charutils import *
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import utils
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from globals import OPTS
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class functional():
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"""
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Functions to write random data values to a random address then read them back and check
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for successful SRAM operation.
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"""
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def __init__(self, sram, spfile, corner):
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self.sram = sram
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self.name = sram.name
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self.word_size = self.sram.word_size
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self.addr_size = self.sram.addr_size
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self.num_cols = self.sram.num_cols
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self.num_rows = self.sram.num_rows
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self.num_banks = self.sram.num_banks
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self.sp_file = spfile
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self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
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self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
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self.total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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# These are the member variables for a simulation
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self.set_corner(corner)
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self.set_spice_constants()
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self.set_stimulus_variables()
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# Number of checks can be changed
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self.num_checks = 1
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def set_corner(self,corner):
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""" Set the corner values """
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self.corner = corner
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(self.process, self.vdd_voltage, self.temperature) = corner
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def set_spice_constants(self):
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""" sets feasible timing parameters """
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self.period = tech.spice["feasible_period"]
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self.slew = tech.spice["rise_time"]*2
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self.load = tech.spice["msflop_in_cap"]*4
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self.gnd_voltage = 0
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def set_stimulus_variables(self):
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""" Variables relevant to functional test """
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self.cycles = 0
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self.written_words = []
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# control signals: only one cs_b for entire multiported sram, one we_b for each write port
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self.cs_b = []
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self.we_b = [[] for port in range(self.total_write)]
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# "end of period" signal used to keep track of when read output should be analyzed
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self.eo_period = []
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# Three dimensional list to handle each addr and data bits for wach port over the number of checks
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self.addresses = [[[] for bit in range(self.addr_size)] for port in range(self.total_write)]
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self.data = [[[] for bit in range(self.word_size)] for port in range(self.total_write)]
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def run(self):
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""" Main function to generate random writes/reads, run spice, and analyze results """
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# Need a NOOP to enable the chip
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# Old code. Is this still necessary?
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self.first_run()
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# Generate write and read signals for spice stimulus
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for i in range(self.num_checks):
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addr = self.gen_addr()
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word = self.gen_data()
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self.write(addr,word)
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self.read(addr,word)
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self.write_functional_stimulus()
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self.stim.run_sim()
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# Extrat DOUT values from spice timing.lis
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read_value = parse_spice_list("timing", "vdout0[0]")
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print("READ VALUE = {}".format(read_value))
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def first_run(self):
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""" First cycle as noop to enable chip """
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self.cycles = self.cycles + 1
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self.cs_b.append(1)
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for port in range(self.total_write):
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self.we_b[port].append(1)
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for port in range(self.total_write):
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for bit in range(self.addr_size):
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self.addresses[port][bit].append(0)
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data[port][bit].append(0)
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def write(self,addr,word,write_port=0):
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""" Generates signals for a write cycle """
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print("Writing {0} to {1}...".format(word,addr))
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self.written_words.append(word)
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self.cycles = self.cycles + 1
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# Write control signals
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self.cs_b.append(0)
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self.we_b[write_port].append(0)
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for port in range(self.total_write):
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if port == write_port:
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continue
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else:
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self.we_b[port].append(1)
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# Write address
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for port in range(self.total_write):
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for bit in range(self.addr_size):
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current_address_bit = int(addr[bit])
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self.addresses[port][bit].append(current_address_bit)
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# Write data
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for port in range(self.total_write):
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for bit in range(self.word_size):
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current_word_bit = int(word[bit])
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self.data[port][bit].append(current_word_bit)
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def read(self,addr,word):
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""" Generates signals for a read cycle """
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print("Reading {0} from {1}...".format(word,addr))
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self.cycles = self.cycles + 2
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# Read control signals
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self.cs_b.append(0)
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for port in range(self.total_write):
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self.we_b[port].append(1)
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# Read address
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for port in range(self.total_write):
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for bit in range(self.addr_size):
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current_address_bit = int(addr[bit])
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self.addresses[port][bit].append(current_address_bit)
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# Data input doesn't matter during read cycle, so arbitrarily set to 0 for simulation
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data[port][bit].append(0)
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# Add idle cycle since read may take more than 1 cycle
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# Idle control signals
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self.cs_b.append(1)
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for port in range(self.total_write):
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self.we_b[port].append(1)
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# Address doesn't matter during idle cycle, but keep the same as read for easier debugging
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for port in range(self.total_write):
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for bit in range(self.addr_size):
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current_address_bit = int(addr[bit])
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self.addresses[port][bit].append(current_address_bit)
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# Data input doesn't matter during idle cycle, so arbitrarily set to 0 for simulation
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for port in range(self.total_write):
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for bit in range(self.word_size):
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self.data[port][bit].append(0)
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# Record the end of the period that the read operation occured in
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self.eo_period.append(self.cycles * self.period)
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def gen_data(self):
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""" Generates a random word to write """
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rand = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(rand,False)
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return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to """
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rand = random.randint(0,(2**self.addr_size)-1)
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addr_bits = self.convert_to_bin(rand,True)
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return addr_bits
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def get_data(self):
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""" Gets an available address and corresponding word """
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# Currently unused but may need later depending on how the functional test develops
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addr = random.choice(self.stored_words.keys())
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word = self.stored_words[addr]
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return (addr,word)
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def convert_to_bin(self,value,is_addr):
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""" Converts addr & word to usable binary values """
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new_value = str.replace(bin(value),"0b","")
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if(is_addr):
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expected_value = self.addr_size
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else:
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expected_value = self.word_size
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for i in range (expected_value - len(new_value)):
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new_value = "0" + new_value
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print("Binary Conversion: {} to {}".format(value, new_value))
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return new_value
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def obtain_cycle_times(self,period):
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""" Generate clock cycle times based on period and number of cycles """
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t_current = 0
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self.cycle_times = []
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for i in range(self.cycles):
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self.cycle_times.append(t_current)
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t_current += period
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def create_port_names(self):
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"""Generates the port names to be used in characterization and sets default simulation target ports"""
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self.write_ports = []
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self.read_ports = []
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self.total_port_num = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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#save a member variable to avoid accessing global. readwrite ports have different control signals.
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self.readwrite_port_num = OPTS.num_rw_ports
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#Generate the port names. readwrite ports are required to be added first for this to work.
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for readwrite_port_num in range(OPTS.num_rw_ports):
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self.read_ports.append(readwrite_port_num)
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self.write_ports.append(readwrite_port_num)
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#This placement is intentional. It makes indexing input data easier. See self.data_values
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for write_port_num in range(OPTS.num_rw_ports, OPTS.num_rw_ports+OPTS.num_w_ports):
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self.write_ports.append(write_port_num)
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for read_port_num in range(OPTS.num_rw_ports+OPTS.num_w_ports, OPTS.num_rw_ports+OPTS.num_w_ports+OPTS.num_r_ports):
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self.read_ports.append(read_port_num)
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self.read_index = []
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.read_index.append("{}".format(port_number))
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port_number += 1
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for port in range(OPTS.num_w_ports):
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_index.append("{}".format(port_number))
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port_number += 1
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def write_functional_stimulus(self):
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#Write Stimulus
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self.obtain_cycle_times(self.period)
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temp_stim = "{0}/stim.sp".format(OPTS.openram_temp)
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self.sf = open(temp_stim,"w")
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self.sf.write("* Functional test stimulus file for {}ns period\n\n".format(self.period))
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self.stim = stimuli(self.sf,self.corner)
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#Write include statements
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self.sram_sp_file = "{}sram.sp".format(OPTS.openram_temp)
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shutil.copy(self.sp_file, self.sram_sp_file)
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self.stim.write_include(self.sram_sp_file)
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#Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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self.stim.write_supply()
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self.create_port_names()
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#Instantiate the SRAM
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_sram(abits=self.addr_size,
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dbits=self.word_size,
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port_info=(self.total_port_num,self.readwrite_port_num,self.read_ports,self.write_ports),
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sram_name=self.name)
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# Add load capacitance to each of the read ports
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self.sf.write("\n* SRAM output loads\n")
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for port in range(self.total_read):
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for bit in range(self.word_size):
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self.sf.write("CD{0}{1} DOUT{0}[{1}] 0 {2}f\n".format(port, bit, self.load))
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# Generate data input bits
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self.sf.write("\n* Generation of data and address signals\n")
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for port in range(self.total_write):
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for bit in range(self.word_size):
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sig_name = "DIN{0}[{1}]".format(port,bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.data[port][bit], self.period, self.slew, 0.05)
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# Generate address bits
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for port in range(self.total_write):
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for bit in range(self.addr_size):
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sig_name = "A{0}[{1}]".format(port,bit)
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self.stim.gen_pwl(sig_name, self.cycle_times, self.addresses[port][bit], self.period, self.slew, 0.05)
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# Generate control signals
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self.sf.write("\n * Generation of control signals\n")
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self.stim.gen_pwl("CSB0", self.cycle_times , self.cs_b, self.period, self.slew, 0.05)
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for port in range(self.total_write):
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self.stim.gen_pwl("WEB{}".format(port), self.cycle_times , self.we_b[port], self.period, self.slew, 0.05)
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# Generate CLK
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self.stim.gen_pulse(sig_name="CLK",
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v1=self.gnd_voltage,
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v2=self.vdd_voltage,
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offset=self.period,
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period=self.period,
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t_rise=self.slew,
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t_fall=self.slew)
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# Generate DOUT value measurements
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self.sf.write("\n * Generation of dout measurements\n")
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for i in range(self.num_checks):
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for port in range(self.total_read):
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for bit in range(self.word_size):
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self.stim.gen_meas_value(meas_name="VDOUT{0}[{1}]".format(port,bit),
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dout="DOUT{0}[{1}]".format(port,bit),
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eo_period=self.eo_period[i],
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slew=self.slew,
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setup=0.05)
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.sf.close()
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@ -213,6 +213,12 @@ class stimuli():
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power_exp,
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t_initial,
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t_final))
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def gen_meas_value(self, meas_name, dout, eo_period, setup, slew):
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t0 = eo_period - setup - 2*slew
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t1 = eo_period - setup - slew
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measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t0, t1)
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self.sf.write(measure_string)
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def write_control(self, end_time):
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""" Write the control cards to run and end the simulation """
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@ -0,0 +1,77 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 22_psram_func_test")
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class psram_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=1,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f.run()
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"""
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 1
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debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f.run
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"""
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#globals.end_openram()
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -11,50 +11,39 @@ import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 22_sram_func_test")
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#@unittest.skip("SKIPPING 22_sram_func_test")
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class sram_func_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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||||
from importlib import reload
|
||||
import characterizer
|
||||
reload(characterizer)
|
||||
from characterizer import delay
|
||||
from characterizer import functional
|
||||
if not OPTS.spice_exe:
|
||||
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
|
||||
|
||||
import sram
|
||||
|
||||
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
|
||||
s = sram.sram(word_size=1,
|
||||
num_words=16,
|
||||
num_banks=1,
|
||||
name="sram_func_test")
|
||||
from sram import sram
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=1,
|
||||
num_words=16,
|
||||
num_banks=1)
|
||||
c.words_per_row=1
|
||||
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank")
|
||||
s = sram(c, name="sram1")
|
||||
|
||||
tempspice = OPTS.openram_temp + "temp.sp"
|
||||
s.sp_write(tempspice)
|
||||
|
||||
probe_address = "1" * s.addr_size
|
||||
probe_data = s.word_size - 1
|
||||
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
|
||||
d = delay(s,tempspice,corner)
|
||||
d.set_probe(probe_address,probe_data)
|
||||
f = functional(s.s, tempspice, corner)
|
||||
f.run()
|
||||
|
||||
# This will exit if it doesn't find a feasible period
|
||||
import tech
|
||||
d.load = tech.spice["msflop_in_cap"]*4
|
||||
d.slew = tech.spice["rise_time"]*2
|
||||
feasible_period = d.find_feasible_period()
|
||||
|
||||
os.remove(tempspice)
|
||||
|
||||
reload(characterizer)
|
||||
globals.end_openram()
|
||||
#globals.end_openram()
|
||||
|
||||
# instantiate a copdsay of the class to actually run the test
|
||||
if __name__ == "__main__":
|
||||
|
|
|
|||
Loading…
Reference in New Issue