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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

This commit is contained in:
Michael Timothy Grimes 2018-08-30 12:42:24 -07:00
parent 77277e19a6 762f2d894c
commit 35ae4a275e
2 changed files with 8 additions and 8 deletions
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12
compiler/gdsMill/gdsMill/vlsiLayout.py
View File

@ -163,7 +163,7 @@ class VlsiLayout:
angle = 0
else:
# MRG: Added negative to make CCW rotate 8/29/18
angle = math.radians(-1.0*float(rotateAngle))
angle = math.radians(float(rotateAngle))
mRotate = matrix([[math.cos(angle),-math.sin(angle),0.0],
[math.sin(angle),math.cos(angle),0.0],
[0.0,0.0,1.0]])
@ -314,6 +314,8 @@ class VlsiLayout:
layoutToAddSref.coordinates = offsetInLayoutUnits
if mirror or rotate:
layoutToAddSref.transFlags = [0,0,0]
# This is NOT the same as the order in the GDS spec!
# It gets written out in gds2writer in the right order though.
# transFlags = (mirror around x-axis, rotation, magnification)
@ -325,8 +327,6 @@ class VlsiLayout:
rotate = 180.0
if mirror=="R270":
rotate = 270.0
layoutToAddSref.transFlags = [0,0,0]
if rotate:
#layoutToAddSref.transFlags = [0,1,0]
layoutToAddSref.rotateAngle = rotate
@ -337,7 +337,7 @@ class VlsiLayout:
layoutToAddSref.transFlags = [1,0,0]
layoutToAddSref.rotateAngle = 180.0
if mirror == "xy" or mirror == "XY": #NOTE: "XY" option will override specified rotate angle
layoutToAddSref.transFlags = [0,1,0]
#layoutToAddSref.transFlags = [0,1,0]
layoutToAddSref.transFlags = [0,0,0]
layoutToAddSref.rotateAngle = 180.0
@ -405,10 +405,10 @@ class VlsiLayout:
if(len(text)%2 == 1):
text = text + '\x00'
textToAdd.textString = text
textToAdd.transFlags[1] = 1
textToAdd.transFlags = [0,0,1]
textToAdd.magFactor = magnification
if rotate:
textToAdd.transFlags[2] = 1
textToAdd.transFlags = [0,1,1]
textToAdd.rotateAngle = rotate
#add the sref to the root structure
self.structures[self.rootStructureName].texts.append(textToAdd)

4
compiler/modules/delay_chain.py
View File

@ -186,7 +186,7 @@ class delay_chain(design.design):
continue
for pin_name in ["vdd", "gnd"]:
pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc(),rotate=0)
self.add_power_pin(pin_name, pin.rc())
else:
# We have an even number of rows, so need to get the last gnd rail
inv = self.driver_inst_list[-1]
@ -195,7 +195,7 @@ class delay_chain(design.design):
continue
pin_name = "gnd"
pin = load.get_pin(pin_name)
self.add_power_pin(pin_name, pin.rc(),rotate=0)
self.add_power_pin(pin_name, pin.rc())
# input is A pin of first inverter