mirror of https://github.com/VLSIDA/OpenRAM.git
Pad the routing grid by a few tracks to add an extra rail
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@ -66,7 +66,8 @@ class router(router_tech):
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self.boundary = self.layout.measureBoundary(self.top_name)
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# These must be un-indexed to get rid of the matrix type
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self.ll = vector(self.boundary[0][0], self.boundary[0][1])
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self.ur = vector(self.boundary[1][0], self.boundary[1][1])
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# Pad the UR by a few tracks to add an extra rail possibly
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self.ur = vector(self.boundary[1][0], self.boundary[1][1]) + self.track_widths.scale(5,5)
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def clear_pins(self):
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"""
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@ -1,6 +1,7 @@
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from tech import drc,layer
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from contact import contact
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from pin_group import pin_group
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from vector import vector
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import debug
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class router_tech:
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@ -35,8 +36,8 @@ class router_tech:
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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debug.info(1,"Track width: "+str(self.track_width))
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self.track_widths = [self.track_width] * 2
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self.track_factor = [1/self.track_width] * 2
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self.track_widths = vector([self.track_width] * 2)
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self.track_factor = vector([1/self.track_width] * 2)
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debug.info(2,"Track factor: {0}".format(self.track_factor))
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# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
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