mirror of https://github.com/VLSIDA/OpenRAM.git
Combine adjacent power supply pins finished
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0544d02ca2
commit
3407163cf1
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@ -12,7 +12,7 @@ class pin_group:
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self.name = name
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# Flag for when it is routed
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self.routed = False
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self.shapes = pin_shapes
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self.pins = pin_shapes
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self.router = router
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# These are the corresponding pin grids for each pin group.
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self.grids = set()
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@ -115,7 +115,7 @@ class pin_group:
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Return the smallest.
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"""
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smallest = None
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for pin in self.shapes:
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for pin in self.pins:
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for enclosure in enclosure_list:
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new_enclosure = self.compute_enclosure(pin, enclosure)
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if smallest == None or new_enclosure.area()<smallest.area():
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@ -130,7 +130,7 @@ class pin_group:
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"""
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smallest_shape = None
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for pin in self.shapes:
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for pin in self.pins:
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# They may not be all on the same layer... in the future.
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zindex=self.router.get_zindex(pin.layer_num)
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(min_width,min_space) = self.router.get_layer_width_space(zindex)
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@ -221,18 +221,77 @@ class pin_group:
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self.enclosure = self.find_smallest_overlapping(enclosure_list)
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if not self.enclosure:
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self.enclosure = self.find_smallest_connector(enclosure_list)
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debug.info(2,"Computed enclosure {0} {1}".format(self.name, self.enclosure))
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debug.info(2,"Computed enclosure {0}\n {1}\n {2}\n {3}".format(self.name, self.pins, self.grids, self.enclosure))
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def add_enclosure(self, cell):
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"""
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Add the enclosure shape to the given cell.
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"""
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debug.info(2,"Adding enclosure {0} {1}".format(self.name, self.enclosure))
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self.router.cell.add_rect(layer=self.enclosure.layer,
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offset=self.enclosure.ll(),
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width=self.enclosure.width(),
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height=self.enclosure.height())
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cell.add_rect(layer=self.enclosure.layer,
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offset=self.enclosure.ll(),
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width=self.enclosure.width(),
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height=self.enclosure.height())
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def adjacent(self, other):
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"""
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Chck if the two pin groups have at least one adjacent pin grid.
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"""
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# We could optimize this to just check the boundaries
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for g1 in self.grids:
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for g2 in other.grids:
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if g1.adjacent(g2):
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return True
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return False
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def convert_pin(self, router):
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#print("PG ",pg)
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# Keep the same groups for each pin
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pin_set = set()
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blockage_set = set()
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for pin in self.pins:
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debug.info(2," Converting {0}".format(pin))
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# Determine which tracks the pin overlaps
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pin_in_tracks=router.convert_pin_to_tracks(self.name, pin)
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pin_set.update(pin_in_tracks)
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# Blockages will be a super-set of pins since it uses the inflated pin shape.
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blockage_in_tracks = router.convert_blockage(pin)
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blockage_set.update(blockage_in_tracks)
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# If we have a blockage, we must remove the grids
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# Remember, this excludes the pin blockages already
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shared_set = pin_set & router.blocked_grids
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if shared_set:
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debug.info(2,"Removing pins {}".format(shared_set))
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shared_set = blockage_set & router.blocked_grids
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if shared_set:
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debug.info(2,"Removing blocks {}".format(shared_set))
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pin_set.difference_update(router.blocked_grids)
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blockage_set.difference_update(router.blocked_grids)
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debug.info(2," pins {}".format(pin_set))
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debug.info(2," blocks {}".format(blockage_set))
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# At least one of the groups must have some valid tracks
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if (len(pin_set)==0 and len(blockage_set)==0):
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self.write_debug_gds("blocked_pin.gds")
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debug.error("Unable to find unblocked pin on grid.")
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# We need to route each of the components, so don't combine the groups
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self.grids = pin_set | blockage_set
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# Add all of the partial blocked grids to the set for the design
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# if they are not blocked by other metal
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#partial_set = blockage_set - pin_set
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#self.blockages = partial_set
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# We should not have added the pins to the blockages,
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# but remove them just in case
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# Partial set may still be in the blockages if there were
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# other shapes disconnected from the pins that were also overlapping
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#route.blocked_grids.difference_update(pin_set)
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@ -152,9 +152,44 @@ class router(router_tech):
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for pin in pin_list:
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self.convert_pins(pin)
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for pin in pin_list:
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self.combine_adjacent_pins(pin)
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#self.write_debug_gds("debug_combine_pins.gds",stop_program=True)
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# Enclose the continguous grid units in a metal rectangle to fix some DRCs
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self.enclose_pins()
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def combine_adjacent_pins(self, pin_name):
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"""
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This checks for simple cases where a pin component already overlaps a supply rail.
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It will add an enclosure to ensure the overlap in wide DRC rule cases.
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"""
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# Make a copy since we are going to reduce this list
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pin_groups = self.pin_groups[pin_name].copy()
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remove_indices = []
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for index1,pg1 in enumerate(self.pin_groups[pin_name]):
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for index2,pg2 in enumerate(self.pin_groups[pin_name]):
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if index1==index2:
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continue
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if pg1.adjacent(pg2):
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debug.info(2,"Combing {0}:\n {1}\n {2}".format(pin_name, pg1.pins, pg2.pins))
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combined = pin_group(pin_name, pg1.pins | pg2.pins, self)
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combined.grids = pg1.grids | pg2.grids
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# check if there are any blockage problems??
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remove_indices.append(index1)
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remove_indices.append(index2)
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pin_groups.append(combined)
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# Remove them in decreasing order to not invalidate the indices
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for i in sorted(remove_indices, reverse=True):
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del pin_groups[i]
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self.pin_groups[pin_name] = pin_groups
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def prepare_blockages(self, pin_name):
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"""
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Reset and add all of the blockages in the design.
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@ -539,50 +574,7 @@ class router(router_tech):
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Convert the pin groups into pin tracks and blockage tracks.
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"""
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for pg in self.pin_groups[pin_name]:
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#print("PG ",pg)
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# Keep the same groups for each pin
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pin_set = set()
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blockage_set = set()
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for pin in pg.shapes:
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debug.info(2," Converting {0}".format(pin))
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# Determine which tracks the pin overlaps
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pin_in_tracks=self.convert_pin_to_tracks(pin_name, pin)
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pin_set.update(pin_in_tracks)
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# Blockages will be a super-set of pins since it uses the inflated pin shape.
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blockage_in_tracks = self.convert_blockage(pin)
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blockage_set.update(blockage_in_tracks)
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# If we have a blockage, we must remove the grids
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# Remember, this excludes the pin blockages already
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shared_set = pin_set & self.blocked_grids
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if shared_set:
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debug.info(2,"Removing pins {}".format(shared_set))
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shared_set = blockage_set & self.blocked_grids
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if shared_set:
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debug.info(2,"Removing blocks {}".format(shared_set))
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pin_set.difference_update(self.blocked_grids)
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blockage_set.difference_update(self.blocked_grids)
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debug.info(2," pins {}".format(pin_set))
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debug.info(2," blocks {}".format(blockage_set))
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# At least one of the groups must have some valid tracks
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if (len(pin_set)==0 and len(blockage_set)==0):
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self.write_debug_gds("blocked_pin.gds")
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debug.error("Unable to find unblocked pin on grid.")
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# We need to route each of the components, so don't combine the groups
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pg.grids = pin_set | blockage_set
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# Add all of the partial blocked grids to the set for the design
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# if they are not blocked by other metal
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#partial_set = blockage_set - pin_set
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#self.pin_blockages[pin_name].append(partial_set)
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# We should not have added the pins to the blockages,
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# but remove them just in case
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# Partial set may still be in the blockages if there were
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# other shapes disconnected from the pins that were also overlapping
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#self.blocked_grids.difference_update(pin_set)
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pg.convert_pin(self)
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@ -99,7 +99,7 @@ class supply_router(router):
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return True
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def route_simple_overlaps(self, pin_name):
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"""
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@ -163,3 +163,17 @@ class vector3d():
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""" Min of both values """
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return vector3d(min(self.x,other.x),min(self.y,other.y),min(self.z,other.z))
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def adjacent(self, other):
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""" Is the one grid adjacent in any planar direction to the other """
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if self == other + vector3d(1,0,0):
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return True
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elif self == other + vector3d(-1,0,0):
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return True
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elif self == other + vector3d(0,1,0):
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return True
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elif self == other + vector3d(0,-1,0):
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return True
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else:
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return False
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