Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases.

compiler/modules/sense_amp_array.py

@@ -30,7 +30,11 @@ class sense_amp_array(design.design):
 
     def create_layout(self):
         self.height = self.amp.height
-        self.width = self.amp.width * self.word_size * self.words_per_row
+        
+        if self.bitcell.width > self.amp.width:
+            self.width = self.bitcell.width * self.word_size * self.words_per_row
+        else:
+            self.width = self.amp.width * self.word_size * self.words_per_row
 
         self.place_sense_amp_array()
         self.add_layout_pins()
@@ -53,6 +57,10 @@ class sense_amp_array(design.design):
         self.amp = self.mod_sense_amp("sense_amp")
         self.add_mod(self.amp)
 
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
+        self.bitcell = self.mod_bitcell()
+        self.add_mod(self.bitcell)
         
     def create_sense_amp_array(self):
         self.local_insts = []
@@ -68,7 +76,10 @@ class sense_amp_array(design.design):
 
     def place_sense_amp_array(self):
             
-        amp_spacing = self.amp.width * self.words_per_row
+        if self.bitcell.width > self.amp.width:
+            amp_spacing = self.bitcell.width * self.words_per_row
+        else:
+            amp_spacing = self.amp.width * self.words_per_row
         for i in range(0,self.word_size):
             amp_position = vector(amp_spacing * i, 0)
             self.local_insts[i].place(amp_position)

compiler/modules/write_driver_array.py

@@ -30,7 +30,12 @@ class write_driver_array(design.design):
         self.create_write_array()
         
     def create_layout(self):
-        self.width = self.columns * self.driver.width
+    
+        if self.bitcell.width > self.driver.width:
+            self.width = self.columns * self.bitcell.width
+        else:
+            self.width = self.columns * self.driver.width
+        
         self.height = self.driver.height
         
         self.place_write_array()
@@ -53,6 +58,11 @@ class write_driver_array(design.design):
         self.mod_write_driver = getattr(c, OPTS.write_driver)
         self.driver = self.mod_write_driver("write_driver")
         self.add_mod(self.driver)
+        
+        c = reload(__import__(OPTS.bitcell))
+        self.mod_bitcell = getattr(c, OPTS.bitcell)
+        self.bitcell = self.mod_bitcell()
+        self.add_mod(self.bitcell)
 
     def create_write_array(self):
         self.driver_insts = {}
@@ -69,9 +79,14 @@ class write_driver_array(design.design):
 
 
     def place_write_array(self):
+        if self.bitcell.width > self.driver.width:
+            driver_spacing = self.bitcell.width
+        else:
+            driver_spacing = self.driver.width
+    
         for i in range(0,self.columns,self.words_per_row):
             index = int(i/self.words_per_row)            
-            base = vector(i * self.driver.width,0)
+            base = vector(i * driver_spacing,0)
             self.driver_insts[index].place(base)
 
             

compiler/tests/09_sense_amp_array_test.py

@@ -17,7 +17,21 @@ class sense_amp_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import sense_amp_array
 
+        # check sense amp array in single port
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
+        a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
+        self.local_check(a)
 
+        debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
+        a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
+        self.local_check(a)
+        
+        # check sense amp array in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.rw_ports = 1
+        OPTS.w_ports = 1
+        OPTS.r_ports = 1
+        
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
         a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
         self.local_check(a)

compiler/tests/10_write_driver_array_test.py

@@ -17,6 +17,7 @@ class write_driver_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         import write_driver_array
 
+        # check write driver array in single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
         a = write_driver_array.write_driver_array(columns=8, word_size=8)
         self.local_check(a)
@@ -25,7 +26,21 @@ class write_driver_test(openram_test):
         a = write_driver_array.write_driver_array(columns=16, word_size=8)
         self.local_check(a)
         
-        globals.end_openram()
+        # check write driver array in multi-port
+        OPTS.bitcell = "pbitcell"
+        OPTS.rw_ports = 1
+        OPTS.w_ports = 1
+        OPTS.r_ports = 1
+        
+        debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
+        a = write_driver_array.write_driver_array(columns=8, word_size=8)
+        self.local_check(a)
+
+        debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
+        a = write_driver_array.write_driver_array(columns=16, word_size=8)
+        self.local_check(a)
+        
+        #globals.end_openram()
 
 # instantiate a copy of the class to actually run the test
 if __name__ == "__main__":