Fixed import errors with mux analytical delay model.

compiler/modules/sense_amp.py

@@ -25,6 +25,7 @@ class sense_amp(design.design):
 
     def input_load(self):
         #Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
+        from tech import spice, parameter
         bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
         return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff   
         

compiler/modules/single_level_column_mux_array.py

@@ -218,7 +218,7 @@ class single_level_column_mux_array(design.design):
                              rotate=90)
 
     def analytical_delay(self, vdd, slew, load=0.0):
-        from tech import spice
+        from tech import spice, parameter
         r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
         #Drains of mux transistors make up capacitance. 
         c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff