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Adding multiported bank_sel pins

This commit is contained in:
Michael Timothy Grimes 2018-09-03 17:35:00 -07:00
parent d3441c7ba4
commit 1e5924d1b7
1 changed files with 5 additions and 4 deletions
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9
compiler/modules/bank.py
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@ -83,7 +83,8 @@ class bank(design.design):
# For more than one bank, we have a bank select and name
# the signals gated_*.
if self.num_banks > 1:
self.add_pin("bank_sel","INPUT")
for port in range(self.total_ports):
self.add_pin("bank_sel{}".format(port),"INPUT")
for k in range(self.total_read):
self.add_pin("s_en{0}".format(k), "INPUT")
for k in range(self.total_write):
@ -514,13 +515,13 @@ class bank(design.design):
return
self.bank_select_inst = []
for k in range(self.total_ports):
self.bank_select_inst.append(self.add_inst(name="bank_select",
for port in range(self.total_ports):
self.bank_select_inst.append(self.add_inst(name="bank_select{}".format(port),
mod=self.bank_select))
temp = []
temp.extend(self.input_control_signals)
temp.append("bank_sel")
temp.append("bank_sel{}".format(port))
temp.extend(self.control_signals)
temp.extend(["vdd", "gnd"])
self.connect_inst(temp)