mirror of https://github.com/VLSIDA/OpenRAM.git
Mirror port 1 column decoder in X and Y
This commit is contained in:
parent
347a68074c
commit
712b71c5ca
|
|
@ -724,7 +724,7 @@ class bank(design.design):
|
|||
|
||||
for port in self.all_ports:
|
||||
if port%2 == 1:
|
||||
mirror = "MY"
|
||||
mirror = "XY"
|
||||
else:
|
||||
mirror = "R0"
|
||||
self.column_decoder_inst[port].place(offset=offsets[port], mirror=mirror)
|
||||
|
|
|
|||
Loading…
Reference in New Issue