mirror of https://github.com/VLSIDA/OpenRAM.git
Change non-preferred route costs.
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commit
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@ -4,8 +4,6 @@ from contact import contact
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import math
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import debug
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from pin_layout import pin_layout
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from vector import vector
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from vector3d import vector3d
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from globals import OPTS
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from router import router
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@ -5,10 +5,10 @@ import math
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import debug
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from globals import OPTS
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from pin_layout import pin_layout
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from vector import vector
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from vector3d import vector3d
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from router import router
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from direction import direction
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import grid
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import grid_utils
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class supply_router(router):
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@ -23,7 +23,12 @@ class supply_router(router):
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either the gds file name or the design itself (by saving to a gds file).
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"""
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router.__init__(self, layers, design, gds_filename)
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# We over-ride the regular router costs to allow
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# more off-direction router in the supply grid
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grid.VIA_COST = 1
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grid.NONPREFERRED_COST = 1
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grid.PREFERRED_COST = 1
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# The list of supply rails (grid sets) that may be routed
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self.supply_rails = {}
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@ -106,7 +106,7 @@ def write_netgen_script(cell_name, sp_name):
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f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name))
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# This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass
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# Is there a more elegant way to add this when needed?
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f.write("flatten class {{{0}.spice bitcell_array}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice bitcell_array}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name))
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f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name))
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