mirror of https://github.com/VLSIDA/OpenRAM.git
Fix write bl name list in replica bitline
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@ -150,7 +150,7 @@ class replica_bitline(design.design):
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self.connect_inst(temp)
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self.wl_list = self.rbl.cell.list_all_wl_names()
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self.bl_list = self.rbl.cell.list_write_bl_names()
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self.bl_list = self.rbl.cell.list_all_bl_names()
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def place_modules(self):
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""" Add all of the module instances in the logical netlist """
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