mirror of https://github.com/VLSIDA/OpenRAM.git
Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done.
This commit is contained in:
Hunter Nichols
parent
5dfa8bc2c6
commit
da6843af5b
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@ -658,15 +658,16 @@ class delay():
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# sys.exit(1)
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#For debugging, skips characterization and returns dummy values.
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# i = 1.0
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# for slew in slews:
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# for load in loads:
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# for k,v in char_data.items():
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# char_data[k].append(i)
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# i+=1.0
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# char_data["min_period"] = i
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# char_data["leakage_power"] = i+1.0
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# return char_data
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char_data = self.char_data
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i = 1.0
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for slew in slews:
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for load in loads:
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for k,v in char_data.items():
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char_data[k].append(i)
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i+=1.0
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char_data["min_period"] = i
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char_data["leakage_power"] = i+1.0
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return char_data
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# 1) Find a feasible period and it's corresponding delays using the trimmed array.
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(feasible_delays_lh, feasible_delays_hl) = self.find_feasible_period()
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@ -12,6 +12,11 @@ class lib:
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""" lib file generation."""
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def __init__(self, out_dir, sram, sp_file, use_model=OPTS.analytical_delay):
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#Temporary Workaround to here to set num of ports. Crashes if set in config file.
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OPTS.num_rw_ports = 2
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#OPTS.num_r_ports = 1
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#OPTS.num_w_ports = 1
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self.out_dir = out_dir
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self.sram = sram
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self.sp_file = sp_file
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@ -112,7 +117,7 @@ class lib:
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self.write_addr_bus(port)
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self.write_control_pins(port) #need to split this into sram and port control signals
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self.write_clk_timing_power(port)
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self.write_clk_timing_power()
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self.write_footer()
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@ -409,8 +414,7 @@ class lib:
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self.write_FF_setuphold()
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self.lib.write(" }\n\n")
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#Port is a temporary input here. I do need a way to dynamically write the control signal here though.
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def write_clk_timing_power(self, port):
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def write_clk_timing_power(self):
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""" Adds clk pin timing results."""
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self.lib.write(" pin(clk){\n")
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@ -419,41 +423,10 @@ class lib:
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# FIXME: This depends on the clock buffer size in the control logic
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self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
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# Find the average power of 1 and 0 bits for writes and reads over all loads/slews
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# Could make it a table, but this is fine for now.
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avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
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avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])
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# Equally divide read/write power between first and second half of clock period
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & clk & !WEb{0}\"; \n".format(port))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & !clk & WEb{0}\"; \n".format(port))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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# Have 0 internal power when disabled, this will be represented as leakage power.
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"CSb{0}\"; \n".format(port))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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#Add power values for the ports. lib generated with this is not syntactically correct. TODO once
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#top level is done
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for port in range(self.total_port_num):
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self.add_clk_control_power(port)
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min_pulse_width = round_time(self.char_results["min_period"])/2.0
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min_period = round_time(self.char_results["min_period"])
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@ -479,7 +452,51 @@ class lib:
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def add_clk_control_power(self, port):
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"""Writes powers under the clock pin group for a specified port"""
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#Web added to read/write ports. Likely to change when control logic finished.
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web_name = ""
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if port in self.write_ports:
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if port in self.read_ports:
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web_name = " & !WEb{0}".format(port)
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avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & clk{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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if port in self.read_ports:
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if port in self.write_ports:
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web_name = " & WEb{0}".format(port)
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avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & !clk{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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# Have 0 internal power when disabled, this will be represented as leakage power.
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"CSb{0}\"; \n".format(port))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def compute_delay(self):
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""" Do the analysis if we haven't characterized the SRAM yet """
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if not hasattr(self,"d"):
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@ -487,11 +504,6 @@ class lib:
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if self.use_model:
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self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
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else:
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#Temporary Workaround to here to set # of ports. Crashes if set in config file.
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#OPTS.num_rw_ports = 0
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#OPTS.num_r_ports = 1
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#OPTS.num_w_ports = 1
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probe_address = "1" * self.sram.addr_size
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probe_data = self.sram.word_size - 1
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self.char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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@ -278,21 +278,21 @@ class setup_hold():
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HL_hold = []
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#For debugging, skips characterization and returns dummy values.
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# i = 1.0
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# for self.related_input_slew in related_slews:
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# for self.constrained_input_slew in constrained_slews:
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# LH_setup.append(i)
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# HL_setup.append(i+1.0)
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# LH_hold.append(i+2.0)
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# HL_hold.append(i+3.0)
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# i+=4.0
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i = 1.0
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for self.related_input_slew in related_slews:
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for self.constrained_input_slew in constrained_slews:
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LH_setup.append(i)
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HL_setup.append(i+1.0)
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LH_hold.append(i+2.0)
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HL_hold.append(i+3.0)
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i+=4.0
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# times = {"setup_times_LH": LH_setup,
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# "setup_times_HL": HL_setup,
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# "hold_times_LH": LH_hold,
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# "hold_times_HL": HL_hold
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# }
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# return times
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times = {"setup_times_LH": LH_setup,
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"setup_times_HL": HL_setup,
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"hold_times_LH": LH_hold,
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"hold_times_HL": HL_hold
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}
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return times
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for self.related_input_slew in related_slews:
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@ -9,4 +9,3 @@ temperatures = [ 25 ]
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output_path = "temp"
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output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
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@ -184,8 +184,8 @@ class openram_test(unittest.TestCase):
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# 4. Check if remaining string matches
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if line1 != line2:
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#Uncomment if you want to see all the individual chars of the two lines
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print(str([i for i in line1]))
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print(str([i for i in line2]))
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#print(str([i for i in line1]))
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#print(str([i for i in line2]))
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if mismatches==0:
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debug.error("Mismatching files:\nfile1={0}\nfile2={1}".format(filename1,filename2))
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mismatches += 1
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