mirror of https://github.com/VLSIDA/OpenRAM.git
Optimizations to pbitcell spacings
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@ -39,6 +39,7 @@ class design(hierarchy_design):
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self.m3_width = drc("minwidth_metal3")
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self.m3_space = drc("metal3_to_metal3")
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self.active_width = drc("minwidth_active")
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self.active_space = drc("active_to_body_active")
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self.contact_width = drc("minwidth_contact")
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self.poly_to_active = drc("poly_to_active")
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@ -197,8 +197,10 @@ class pbitcell(design.design):
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self.inverter_nmos_ypos = self.port_ypos
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# spacing between ports
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self.bitline_offset = -self.active_width + 0.5*contact.m1m2.height + self.m2_space + self.m2_width
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self.port_spacing = self.bitline_offset + self.m2_space
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self.bitline_offset = -0.5*self.readwrite_nmos.active_width + 0.5*contact.m1m2.height + self.m2_space + self.m2_width
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m2_constraint = self.bitline_offset + self.m2_space + 0.5*contact.m1m2.height - 0.5*self.readwrite_nmos.active_width
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self.rw_w_spacing = max(self.active_space, self.m1_space, m2_constraint)
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self.r_spacing = self.bitline_offset + self.m2_space
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# spacing between cross coupled inverters
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self.inverter_to_inverter_spacing = contact.poly.height + self.m1_space
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@ -236,9 +238,9 @@ class pbitcell(design.design):
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self.topmost_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset
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self.leftmost_xpos = -0.5*self.inverter_to_inverter_spacing - self.inverter_nmos.active_width \
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- self.num_rw_ports*(self.readwrite_nmos.active_width + self.port_spacing) \
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- self.num_w_ports*(self.write_nmos.active_width + self.port_spacing) \
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- self.num_r_ports*(self.read_port_width + self.port_spacing) \
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- self.num_rw_ports*(self.readwrite_nmos.active_width + self.rw_w_spacing) \
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- self.num_w_ports*(self.write_nmos.active_width + self.rw_w_spacing) \
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- self.num_r_ports*(self.read_port_width + self.r_spacing) \
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- self.bitline_offset - 0.5*self.m2_width
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self.width = -2*self.leftmost_xpos
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@ -370,11 +372,11 @@ class pbitcell(design.design):
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for k in range(0,self.num_rw_ports):
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# calculate read/write transistor offsets
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left_readwrite_transistor_xpos = self.left_building_edge \
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- (k+1)*self.port_spacing \
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- (k+1)*self.rw_w_spacing \
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- (k+1)*self.readwrite_nmos.active_width
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right_readwrite_transistor_xpos = self.right_building_edge \
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+ (k+1)*self.port_spacing \
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+ (k+1)*self.rw_w_spacing \
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+ k*self.readwrite_nmos.active_width
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# place read/write transistors
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@ -392,7 +394,7 @@ class pbitcell(design.design):
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height=self.m1_width)
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# add pins for RWBL and RWBR
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rwbl_xpos = left_readwrite_transistor_xpos - self.bitline_offset + self.m2_width
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rwbl_xpos = left_readwrite_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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self.rwbl_positions[k] = vector(rwbl_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.rw_bl_names[k],
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layer="metal2",
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@ -400,7 +402,7 @@ class pbitcell(design.design):
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width=drc["minwidth_metal2"],
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height=self.height)
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rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width + self.bitline_offset - self.m2_width
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rwbr_xpos = right_readwrite_transistor_xpos + self.readwrite_nmos.active_width + self.bitline_offset - 0.5*self.m2_width
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self.rwbr_positions[k] = vector(rwbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.rw_br_names[k],
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layer="metal2",
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@ -447,11 +449,11 @@ class pbitcell(design.design):
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# Add transistors
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# calculate write transistor offsets
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left_write_transistor_xpos = self.left_building_edge \
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- (k+1)*self.port_spacing \
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- (k+1)*self.rw_w_spacing \
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- (k+1)*self.write_nmos.active_width
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right_write_transistor_xpos = self.right_building_edge \
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+ (k+1)*self.port_spacing \
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+ (k+1)*self.rw_w_spacing \
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+ k*self.write_nmos.active_width
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# add write transistors
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@ -469,7 +471,7 @@ class pbitcell(design.design):
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height=self.m1_width)
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# add pins for WBL and WBR
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wbl_xpos = left_write_transistor_xpos - self.bitline_offset + self.m2_width
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wbl_xpos = left_write_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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self.wbl_positions[k] = vector(wbl_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.w_bl_names[k],
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layer="metal2",
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@ -477,7 +479,7 @@ class pbitcell(design.design):
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width=drc["minwidth_metal2"],
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height=self.height)
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wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset - self.m2_width
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wbr_xpos = right_write_transistor_xpos + self.write_nmos.active_width + self.bitline_offset - 0.5*self.m2_width
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self.wbr_positions[k] = vector(wbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.w_br_names[k],
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layer="metal2",
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@ -541,11 +543,11 @@ class pbitcell(design.design):
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for k in range(0,self.num_r_ports):
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# calculate transistor offsets
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left_read_transistor_xpos = self.left_building_edge \
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- (k+1)*self.port_spacing \
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- (k+1)*self.r_spacing \
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- (k+1)*self.read_port_width
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right_read_transistor_xpos = self.right_building_edge \
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+ (k+1)*self.port_spacing \
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+ (k+1)*self.r_spacing \
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+ k*self.read_port_width
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# add read-access transistors
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@ -568,7 +570,7 @@ class pbitcell(design.design):
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height=self.m1_width)
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# add pins for RBL and RBR
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rbl_xpos = left_read_transistor_xpos - self.bitline_offset + self.m2_width
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rbl_xpos = left_read_transistor_xpos - self.bitline_offset + 0.5*self.m2_width
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self.rbl_positions[k] = vector(rbl_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.r_bl_names[k],
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layer="metal2",
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@ -576,7 +578,7 @@ class pbitcell(design.design):
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width=drc["minwidth_metal2"],
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height=self.height)
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rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset - self.m2_width
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rbr_xpos = right_read_transistor_xpos + self.read_port_width + self.bitline_offset - 0.5*self.m2_width
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self.rbr_positions[k] = vector(rbr_xpos, self.center_ypos)
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self.add_layout_pin_rect_center(text=self.r_br_names[k],
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layer="metal2",
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@ -692,7 +694,11 @@ class pbitcell(design.design):
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=position)
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supply_offset = vector(position.x, self.gnd_position.y)
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if position.x > 0:
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contact_correct = 0.5*contact.m1m2.height
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else:
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contact_correct = -0.5*contact.m1m2.height
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supply_offset = vector(position.x + contact_correct, self.gnd_position.y)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=supply_offset,
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rotate=90)
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