mirror of https://github.com/VLSIDA/OpenRAM.git
Add initial support and unit tests for 2 port SRAM
This commit is contained in:
Matt Guthaus
parent
6ac5adaeca
commit
3221d3e744
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@ -61,7 +61,8 @@ class bank(design.design):
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#self.add_lvs_correspondence_points()
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# Remember the bank center for further placement
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self.bank_center=self.offset_all_coordinates().scale(-1,-1)
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self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
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self.bank_array_ur = self.bitcell_array_inst.ur()
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self.DRC_LVS()
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@ -43,10 +43,10 @@ class sram_1bank(sram_base):
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self.data_dff_insts = self.create_data_dff()
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def place_modules(self):
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def place_instances(self):
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"""
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This places the modules for a single bank SRAM with control
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logic.
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This places the instances for a single bank SRAM with control
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logic and up to 2 ports.
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"""
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# No orientation or offset
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@ -57,39 +57,70 @@ class sram_1bank(sram_base):
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# the sense amps/column mux and cell array)
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# The x-coordinate is placed to allow a single clock wire (plus an extra pitch)
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# up to the row address DFFs.
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for port in self.all_ports:
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control_pos = vector(-self.control_logic_rw.width - 2*self.m2_pitch,
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self.bank.bank_center.y - self.control_logic_rw.control_logic_center.y)
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self.control_logic_insts[port].place(control_pos)
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# The row address bits are placed above the control logic aligned on the right.
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row_addr_pos = vector(self.control_logic_insts[0].rx() - self.row_addr_dff.width,
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self.control_logic_insts[0].uy())
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self.row_addr_dff_insts[port].place(row_addr_pos)
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# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
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data_gap = -self.m2_pitch*(self.word_size+1)
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# Add the column address below the bank under the control
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# The column address flops are aligned with the data flops
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if self.col_addr_dff:
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col_addr_pos = vector(self.bank.bank_center.x - self.col_addr_dff.width - self.bank.central_bus_width,
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data_gap - self.col_addr_dff.height)
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self.col_addr_dff_insts[port].place(col_addr_pos)
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# Add the data flops below the bank to the right of the center of bank:
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# This relies on the center point of the bank:
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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data_pos = vector(self.bank.bank_center.x,
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data_gap - self.data_dff.height)
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self.data_dff_insts[port].place(data_pos)
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# two supply rails are already included in the bank, so just 2 here.
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# self.width = self.bank.width + self.control_logic.width + 2*self.supply_rail_pitch
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# self.height = self.bank.height
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control_pos = [None]*len(self.all_ports)
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row_addr_pos = [None]*len(self.all_ports)
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col_addr_pos = [None]*len(self.all_ports)
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data_pos = [None]*len(self.all_ports)
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# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
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data_gap = self.m2_pitch*(self.word_size+1)
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# Port 0
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port = 0
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control_pos[port] = vector(-self.control_logic_insts[port].width - 2*self.m2_pitch,
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self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
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self.control_logic_insts[port].place(control_pos[port])
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# The row address bits are placed above the control logic aligned on the right.
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row_addr_pos[port] = vector(self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width,
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self.control_logic_insts[port].uy())
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self.row_addr_dff_insts[port].place(row_addr_pos[port])
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# Add the col address flops below the bank to the left of the lower-left of bank array
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if self.col_addr_dff:
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col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.central_bus_width,
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-data_gap - self.col_addr_dff_insts[port].height)
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self.col_addr_dff_insts[port].place(col_addr_pos[port])
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# Add the data flops below the bank to the right of the lower-left of bank array
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# This relies on the lower-left of the array of the bank
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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if port in self.write_ports:
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data_pos[port] = vector(self.bank.bank_array_ll.x,
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-data_gap - self.data_dff_insts[port].height)
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self.data_dff_insts[port].place(data_pos[port])
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# Port 1
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port = 1
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control_pos[port] = vector(self.bank_inst.rx() + self.control_logic_insts[port].width + 2*self.m2_pitch,
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self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
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self.control_logic_insts[port].place(control_pos[port], mirror="MY")
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# The row address bits are placed above the control logic aligned on the left.
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row_addr_pos[port] = vector(self.bank_inst.rx() + self.row_addr_dff_insts[port].width,
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self.control_logic_insts[port].uy())
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self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="MY")
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# Add the col address flops above the bank to the right of the upper-right of bank array
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if self.col_addr_dff:
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col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.central_bus_width,
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self.bank_inst.uy() + data_gap + self.col_addr_dff_insts[port].height)
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self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX")
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# Add the data flops above the bank to the left of the upper-right of bank array
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# This relies on the upper-right of the array of the bank
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# decoder in upper left, bank in upper right, sensing in lower right.
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# These flops go below the sensing and leave a gap to channel route to the
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# sense amps.
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if port in self.write_ports:
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data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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self.bank.uy() + data_gap + self.data_dff_insts[port].height)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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def add_layout_pins(self):
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"""
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Add the top-level pins for a single bank SRAM with control.
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@ -114,7 +145,7 @@ class sram_1bank(sram_base):
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for bit in range(self.word_size):
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self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit))
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def route(self):
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def route_layout(self):
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""" Route a single bank SRAM """
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self.add_layout_pins()
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@ -151,11 +182,12 @@ class sram_1bank(sram_base):
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dff_clk_pos = dff_clk_pin.center()
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mid_pos = vector(bank_clk_buf_pos.x, dff_clk_pos.y)
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self.add_wire(("metal3","via2","metal2"),[dff_clk_pos, mid_pos, bank_clk_buf_pos])
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data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
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data_dff_clk_pos = data_dff_clk_pin.center()
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mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y)
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self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos])
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if port in self.write_ports:
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data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
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data_dff_clk_pos = data_dff_clk_pin.center()
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mid_pos = vector(bank_clk_buf_pos.x, data_dff_clk_pos.y)
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self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, bank_clk_buf_pos])
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# This uses a metal2 track to the right of the control/row addr DFF
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# to route vertically.
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@ -75,8 +75,9 @@ class sram_base(design):
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def create_layout(self):
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""" Layout creation """
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self.place_modules()
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self.route()
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self.place_instances()
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self.route_layout()
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self.add_lvs_correspondence_points()
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@ -369,9 +370,13 @@ class sram_base(design):
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def create_data_dff(self):
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""" Add and place all data flops """
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insts = []
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for port in self.write_ports:
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insts.append(self.add_inst(name="data_dff{}".format(port),
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mod=self.data_dff))
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for port in self.all_ports:
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if port in self.write_ports:
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insts.append(self.add_inst(name="data_dff{}".format(port),
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mod=self.data_dff))
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else:
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insts.append(None)
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continue
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# inputs, outputs/output/bar
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inputs = []
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@ -0,0 +1,43 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank, 2 port SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class sram_1bank_2mux_1rw_1r_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=2
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debug.info(1, "Single bank, two way column mux 1rw, 1r with control logic")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -0,0 +1,43 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank, 2 port SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class sram_1bank_nomux_1rw_1r_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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c = sram_config(word_size=4,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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debug.info(1, "Single bank, no column mux 1rw, 1r with control logic")
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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