mirror of https://github.com/VLSIDA/OpenRAM.git
Altering control logic for multiport. Netlist changes only.
This commit is contained in:
Michael Timothy Grimes
parent
bfc855b8b1
commit
7dfd37f79c
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@ -24,6 +24,8 @@ class control_logic(design.design):
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debug.info(1, "Creating {}".format(self.name))
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self.num_rows = num_rows
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self.total_write = OPTS.num_rw_ports + OPTS.num_w_ports
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self.total_read = OPTS.num_rw_ports + OPTS.num_r_ports
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -61,7 +63,7 @@ class control_logic(design.design):
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dff = dff_inv()
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dff_height = dff.height
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self.ctrl_dff_array = dff_inv_array(rows=2,columns=1)
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self.ctrl_dff_array = dff_inv_array(rows=1+self.total_write,columns=1)
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self.add_mod(self.ctrl_dff_array)
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self.nand2 = pnand2(height=dff_height)
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@ -96,14 +98,27 @@ class control_logic(design.design):
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""" Setup bus names, determine the size of the busses etc """
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# List of input control signals
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self.input_list =["csb","web0"]
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self.dff_output_list =["cs_bar", "cs", "we_bar", "we"]
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self.input_list =["csb"]
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for port in range(self.total_write):
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self.input_list.append("web{}".format(port))
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self.dff_output_list =["cs_bar", "cs"]
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for port in range(self.total_write):
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self.dff_output_list.append("we_bar{}".format(port))
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self.dff_output_list.append("we{}".format(port))
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# list of output control signals (for making a vertical bus)
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self.internal_bus_list = ["clk_buf", "clk_buf_bar", "we", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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# Outputs to the bank
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self.output_list = ["s_en0", "w_en0", "clk_buf_bar", "clk_buf"]
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self.output_list = ["s_en0"]
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for port in range(self.total_write):
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self.output_list.append("w_en{}".format(port))
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self.output_list.append("clk_buf_bar")
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self.output_list.append("clk_buf")
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self.supply_list = ["vdd", "gnd"]
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@ -302,23 +317,31 @@ class control_logic(design.design):
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def create_we_row(self):
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# input: WE, CS output: w_en_bar
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self.w_en_bar_inst=self.add_inst(name="nand3_w_en_bar",
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mod=self.nand3)
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self.connect_inst(["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"])
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self.w_en_bar_inst = []
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for port in range(self.total_write):
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self.w_en_bar_inst.append(self.add_inst(name="nand3_w_en_bar{}".format(port),
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mod=self.nand3))
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self.connect_inst(["clk_buf_bar", "cs", "we{}".format(port), "w_en_bar{}".format(port), "vdd", "gnd"])
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# input: w_en_bar, output: pre_w_en
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self.pre_w_en_inst=self.add_inst(name="inv_pre_w_en",
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mod=self.inv1)
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self.connect_inst(["w_en_bar", "pre_w_en", "vdd", "gnd"])
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self.pre_w_en_inst = []
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for port in range(self.total_write):
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self.pre_w_en_inst.append(self.add_inst(name="inv_pre_w_en{}".format(port),
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mod=self.inv1))
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self.connect_inst(["w_en_bar{}".format(port), "pre_w_en{}".format(port), "vdd", "gnd"])
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# BUFFER INVERTERS FOR W_EN
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self.pre_w_en_bar_inst=self.add_inst(name="inv_pre_w_en_bar",
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mod=self.inv2)
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self.connect_inst(["pre_w_en", "pre_w_en_bar", "vdd", "gnd"])
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self.pre_w_en_bar_inst = []
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for port in range(self.total_write):
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self.pre_w_en_bar_inst.append(self.add_inst(name="inv_pre_w_en_bar{}".format(port),
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mod=self.inv2))
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self.connect_inst(["pre_w_en{}".format(port), "pre_w_en_bar{}".format(port), "vdd", "gnd"])
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self.w_en_inst=self.add_inst(name="inv_w_en2",
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mod=self.inv8)
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self.connect_inst(["pre_w_en_bar", "w_en0", "vdd", "gnd"])
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self.w_en_inst = []
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for port in range(self.total_write):
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self.w_en_inst.append(self.add_inst(name="inv_w_en2_{}".format(port),
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mod=self.inv8))
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self.connect_inst(["pre_w_en_bar{}".format(port), "w_en{}".format(port), "vdd", "gnd"])
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def place_we_row(self,row):
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@ -326,26 +349,26 @@ class control_logic(design.design):
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(y_off,mirror)=self.get_offset(row)
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w_en_bar_offset = vector(x_off, y_off)
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self.w_en_bar_inst.place(offset=w_en_bar_offset,
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self.w_en_bar_inst[0].place(offset=w_en_bar_offset,
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mirror=mirror)
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x_off += self.nand3.width
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pre_w_en_offset = vector(x_off, y_off)
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self.pre_w_en_inst.place(offset=pre_w_en_offset,
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self.pre_w_en_inst[0].place(offset=pre_w_en_offset,
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mirror=mirror)
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x_off += self.inv1.width
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pre_w_en_bar_offset = vector(x_off, y_off)
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self.pre_w_en_bar_inst.place(offset=pre_w_en_bar_offset,
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self.pre_w_en_bar_inst[0].place(offset=pre_w_en_bar_offset,
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mirror=mirror)
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x_off += self.inv2.width
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w_en_offset = vector(x_off, y_off)
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self.w_en_inst.place(offset=w_en_offset,
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self.w_en_inst[0].place(offset=w_en_offset,
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mirror=mirror)
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x_off += self.inv8.width
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self.row_end_inst.append(self.w_en_inst)
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self.row_end_inst.append(self.w_en_inst[0])
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def route_rbl_in(self):
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@ -423,19 +446,19 @@ class control_logic(design.design):
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def route_wen(self):
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wen_map = zip(["A", "B", "C"], ["clk_buf_bar", "cs", "we"])
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self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets)
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self.connect_vertical_bus(wen_map, self.w_en_bar_inst[0], self.rail_offsets)
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# Connect the NAND3 output to the inverter
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# The pins are assumed to extend all the way to the cell edge
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w_en_bar_pos = self.w_en_bar_inst.get_pin("Z").center()
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inv_in_pos = self.pre_w_en_inst.get_pin("A").center()
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w_en_bar_pos = self.w_en_bar_inst[0].get_pin("Z").center()
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inv_in_pos = self.pre_w_en_inst[0].get_pin("A").center()
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mid1 = vector(inv_in_pos.x,w_en_bar_pos.y)
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self.add_path("metal1",[w_en_bar_pos,mid1,inv_in_pos])
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self.add_path("metal1",[self.pre_w_en_inst.get_pin("Z").center(), self.pre_w_en_bar_inst.get_pin("A").center()])
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self.add_path("metal1",[self.pre_w_en_bar_inst.get_pin("Z").center(), self.w_en_inst.get_pin("A").center()])
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self.add_path("metal1",[self.pre_w_en_inst[0].get_pin("Z").center(), self.pre_w_en_bar_inst[0].get_pin("A").center()])
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self.add_path("metal1",[self.pre_w_en_bar_inst[0].get_pin("Z").center(), self.w_en_inst[0].get_pin("A").center()])
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self.connect_output(self.w_en_inst, "Z", "w_en0")
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self.connect_output(self.w_en_inst[0], "Z", "w_en0")
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def route_sen(self):
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rbl_out_pos = self.rbl_inst.get_pin("out").bc()
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@ -34,9 +34,7 @@ class sram_1bank(sram_base):
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self.bank_inst=self.create_bank(0)
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self.control_logic_inst = [None] * self.total_ports
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for port in range(self.total_ports):
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self.control_logic_inst[port] = self.create_control_logic(port)
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self.control_logic_inst = self.create_control_logic()
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self.row_addr_dff_inst = self.create_row_addr_dff()
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@ -61,11 +59,11 @@ class sram_1bank(sram_base):
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# up to the row address DFFs.
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control_pos = vector(-self.control_logic.width - 2*self.m2_pitch,
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self.bank.bank_center.y - self.control_logic.control_logic_center.y)
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self.control_logic_inst[0].place(control_pos)
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self.control_logic_inst.place(control_pos)
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# The row address bits are placed above the control logic aligned on the right.
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row_addr_pos = vector(self.control_logic_inst[0].rx() - self.row_addr_dff.width,
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self.control_logic_inst[0].uy())
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row_addr_pos = vector(self.control_logic_inst.rx() - self.row_addr_dff.width,
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self.control_logic_inst.uy())
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self.row_addr_dff_inst.place(row_addr_pos)
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# This is M2 pitch even though it is on M1 to help stem via spacings on the trunk
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@ -97,7 +95,7 @@ class sram_1bank(sram_base):
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"""
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# Connect the control pins as inputs
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for n in self.control_logic_inputs + ["clk"]:
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self.copy_layout_pin(self.control_logic_inst[0], n)
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self.copy_layout_pin(self.control_logic_inst, n)
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for i in range(self.word_size):
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dout_name = "dout0[{}]".format(i)
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@ -136,7 +134,7 @@ class sram_1bank(sram_base):
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""" Route the clock network """
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# This is the actual input to the SRAM
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self.copy_layout_pin(self.control_logic_inst[0], "clk")
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self.copy_layout_pin(self.control_logic_inst, "clk")
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# Connect all of these clock pins to the clock in the central bus
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# This is something like a "spine" clock distribution. The two spines
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@ -160,7 +158,7 @@ class sram_1bank(sram_base):
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# This uses a metal2 track to the right of the control/row addr DFF
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# to route vertically.
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control_clk_buf_pin = self.control_logic_inst[0].get_pin("clk_buf")
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control_clk_buf_pin = self.control_logic_inst.get_pin("clk_buf")
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control_clk_buf_pos = control_clk_buf_pin.rc()
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row_addr_clk_pin = self.row_addr_dff_inst.get_pin("clk")
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row_addr_clk_pos = row_addr_clk_pin.rc()
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@ -179,7 +177,7 @@ class sram_1bank(sram_base):
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top_instances = [self.bank_inst,
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self.row_addr_dff_inst,
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self.data_dff_inst,
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self.control_logic_inst[0]]
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self.control_logic_inst]
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if self.col_addr_dff:
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top_instances.append(self.col_addr_dff_inst)
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@ -195,7 +193,7 @@ class sram_1bank(sram_base):
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top_instances = [self.bank_inst,
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self.row_addr_dff_inst,
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self.data_dff_inst,
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self.control_logic_inst[0]]
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self.control_logic_inst]
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if self.col_addr_dff:
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top_instances.append(self.col_addr_dff_inst)
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@ -269,7 +267,7 @@ class sram_1bank(sram_base):
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def route_control_logic(self):
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""" Route the outputs from the control logic module """
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for n in self.control_logic_outputs:
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src_pin = self.control_logic_inst[0].get_pin(n)
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src_pin = self.control_logic_inst.get_pin(n)
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dest_pin = self.bank_inst.get_pin(n)
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self.connect_rail_from_left_m2m3(src_pin, dest_pin)
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self.add_via_center(layers=("metal1","via1","metal2"),
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@ -336,7 +334,7 @@ class sram_1bank(sram_base):
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"""
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for n in self.control_logic_outputs:
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pin = self.control_logic_inst[0].get_pin(n)
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pin = self.control_logic_inst.get_pin(n)
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self.add_label(text=n,
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layer=pin.layer,
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offset=pin.center())
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@ -375,14 +375,19 @@ class sram_base(design):
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self.connect_inst(inputs + outputs + ["clk_buf", "vdd", "gnd"])
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return inst
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def create_control_logic(self, port):
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def create_control_logic(self):
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""" Add and place control logic """
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inst = self.add_inst(name="control",
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mod=self.control_logic)
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self.connect_inst(["csb", "web{}".format(port), "clk",
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"s_en{}".format(port), "w_en{}".format(port), "clk_buf_bar", "clk_buf",
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"vdd", "gnd"])
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temp = ["csb"]
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for port in range(self.total_write):
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temp.append("web{}".format(port))
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temp.extend(["clk", "s_en0"])
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for port in range(self.total_write):
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temp.append("w_en{}".format(port))
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temp.extend(["clk_buf_bar", "clk_buf", "vdd", "gnd"])
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self.connect_inst(temp)
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#self.connect_inst(self.control_logic_inputs + self.control_logic_outputs + ["vdd", "gnd"])
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return inst
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