mirror of https://github.com/VLSIDA/OpenRAM.git
Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes.
This commit is contained in:
Michael Timothy Grimes
parent
f1560375fc
commit
648e57d195
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@ -53,6 +53,7 @@ class bank(design.design):
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self.add_modules()
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self.create_modules()
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def create_layout(self):
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self.place_modules()
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self.setup_routing_constraints()
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@ -65,17 +66,22 @@ class bank(design.design):
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self.bank_center=self.offset_all_coordinates().scale(-1,-1)
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self.DRC_LVS()
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def add_pins(self):
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self.read_index = []
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self.port_id = []
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.read_index.append("{}".format(port_number))
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self.port_id.append("rw")
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port_number += 1
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for port in range(OPTS.num_w_ports):
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self.port_id.append("w")
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_index.append("{}".format(port_number))
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self.port_id.append("r")
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port_number += 1
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""" Adding pins for Bank module"""
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@ -94,14 +100,17 @@ class bank(design.design):
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if self.num_banks > 1:
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for port in range(self.total_ports):
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self.add_pin("bank_sel{}".format(port),"INPUT")
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self.add_pin("s_en", "INPUT")
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for port in range(self.total_read):
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self.add_pin("s_en{0}".format(port), "INPUT")
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for port in range(self.total_write):
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self.add_pin("w_en{0}".format(port), "INPUT")
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for pin in ["clk_buf_bar","clk_buf"]:
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self.add_pin(pin,"INPUT")
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for port in range(self.total_ports):
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self.add_pin("clk_buf_bar{0}".format(port),"INPUT")
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self.add_pin("clk_buf{0}".format(port),"INPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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def route_layout(self):
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""" Create routing amoung the modules """
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self.route_central_bus()
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@ -118,6 +127,7 @@ class bank(design.design):
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self.route_bank_select()
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self.route_vdd_gnd()
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def create_modules(self):
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""" Add modules. The order should not matter! """
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@ -155,10 +165,10 @@ class bank(design.design):
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self.place_row_decoder()
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self.place_wordline_driver()
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self.place_column_decoder()
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self.place_bank_select()
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def compute_sizes(self):
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""" Computes the required sizes to create the bank """
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@ -180,13 +190,25 @@ class bank(design.design):
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# Number of control lines in the bus
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self.num_control_lines = 4
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# The order of the control signals on the control bus:
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self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en"]
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self.input_control_signals = []
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port_num = 0
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for port in range(OPTS.num_rw_ports):
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self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_w_ports):
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self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "w_en{}".format(port_num)])
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port_num += 1
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for port in range(OPTS.num_r_ports):
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self.input_control_signals.append(["clk_buf{}".format(port_num), "clk_buf_bar{}".format(port_num), "s_en{}".format(port_num)])
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port_num += 1
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# These will be outputs of the gaters if this is multibank, if not, normal signals.
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if self.num_banks > 1:
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self.control_signals = ["gated_"+str for str in self.input_control_signals]
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else:
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self.control_signals = self.input_control_signals
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self.control_signals = []
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for port in range(self.total_ports):
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if self.num_banks > 1:
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self.control_signals.append(["gated_"+str for str in self.input_control_signals[port]])
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else:
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self.control_signals.append(self.input_control_signals[port])
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# The central bus is the column address (one hot) and row address (binary)
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if self.col_addr_size>0:
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self.num_col_addr_lines = 2**self.col_addr_size
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@ -291,6 +313,7 @@ class bank(design.design):
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temp.append("gnd")
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self.connect_inst(temp)
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def place_bitcell_array(self):
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""" Placing Bitcell Array """
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self.bitcell_array_inst.place(vector(0,0))
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@ -307,9 +330,10 @@ class bank(design.design):
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for i in range(self.num_cols):
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temp.append(self.read_bl_list[port]+"[{0}]".format(i))
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temp.append(self.read_br_list[port]+"[{0}]".format(i))
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temp.extend([self.prefix+"clk_buf_bar", "vdd"])
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temp.extend([self.prefix+"clk_buf_bar{0}".format(self.read_index[port]), "vdd"])
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self.connect_inst(temp)
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def place_precharge_array(self):
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""" Placing Precharge """
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@ -319,6 +343,7 @@ class bank(design.design):
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# The enclosure is for the well and the spacing is to the bitcell wells
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y_offset = self.bitcell_array.height + self.m2_gap
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self.precharge_array_inst[port].place(vector(0,y_offset))
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def create_column_mux_array(self):
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""" Creating Column Mux when words_per_row > 1 . """
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@ -342,6 +367,7 @@ class bank(design.design):
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temp.append("gnd")
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self.connect_inst(temp)
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def place_column_mux_array(self):
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""" Placing Column Mux when words_per_row > 1 . """
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if self.col_addr_size > 0:
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@ -353,6 +379,7 @@ class bank(design.design):
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for port in range(self.total_ports):
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y_offset = self.column_mux_height
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self.col_mux_array_inst[port].place(vector(0,y_offset).scale(-1,-1))
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def create_sense_amp_array(self):
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""" Creating Sense amp """
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@ -372,9 +399,10 @@ class bank(design.design):
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temp.append(self.read_bl_list[port]+"_out[{0}]".format(bit))
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temp.append(self.read_br_list[port]+"_out[{0}]".format(bit))
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temp.extend([self.prefix+"s_en", "vdd", "gnd"])
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temp.extend([self.prefix+"s_en{}".format(port), "vdd", "gnd"])
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self.connect_inst(temp)
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def place_sense_amp_array(self):
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""" Placing Sense amp """
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@ -382,6 +410,7 @@ class bank(design.design):
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for port in range(self.total_read):
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y_offset = self.column_mux_height + self.sense_amp_array.height + self.m2_gap
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self.sense_amp_array_inst[port].place(vector(0,y_offset).scale(-1,-1))
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def create_write_driver_array(self):
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""" Creating Write Driver """
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@ -404,6 +433,7 @@ class bank(design.design):
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temp.extend([self.prefix+"w_en{0}".format(port), "vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_driver_array(self):
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""" Placing Write Driver """
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@ -412,7 +442,6 @@ class bank(design.design):
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y_offset = self.sense_amp_array.height + self.column_mux_height \
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+ self.m2_gap + self.write_driver_array.height
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self.write_driver_array_inst[port].place(vector(0,y_offset).scale(-1,-1))
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def create_row_decoder(self):
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@ -431,6 +460,7 @@ class bank(design.design):
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_row_decoder(self):
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""" Place the hierarchical row decoder """
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@ -459,11 +489,12 @@ class bank(design.design):
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temp.append("dec_out{0}[{1}]".format(port,row))
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for row in range(self.num_rows):
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temp.append(self.total_wl_list[port]+"[{0}]".format(row))
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temp.append(self.prefix+"clk_buf")
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temp.append(self.prefix+"clk_buf{0}".format(port))
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temp.append("vdd")
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temp.append("gnd")
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self.connect_inst(temp)
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def place_wordline_driver(self):
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""" Place the Wordline Driver """
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@ -505,6 +536,7 @@ class bank(design.design):
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_column_decoder(self):
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"""
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Place a 2:4 or 3:8 column address decoder.
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@ -532,12 +564,13 @@ class bank(design.design):
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mod=self.bank_select))
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temp = []
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temp.extend(self.input_control_signals)
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temp.extend(self.input_control_signals[port])
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temp.append("bank_sel{}".format(port))
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temp.extend(self.control_signals)
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temp.extend(self.control_signals[port])
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temp.extend(["vdd", "gnd"])
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self.connect_inst(temp)
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def place_bank_select(self):
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""" Place the bank select logic. """
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@ -548,9 +581,9 @@ class bank(design.design):
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for port in range(self.total_ports):
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x_off = -(self.row_decoder.width + self.central_bus_width + self.wordline_driver.width)
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if self.col_addr_size > 0:
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y_off = min(self.col_decoder_inst[0].by(), self.col_mux_array_inst[0].by())
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y_off = min(self.col_decoder_inst[port].by(), self.col_mux_array_inst[port].by())
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else:
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y_off = self.row_decoder_inst[0].by()
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y_off = self.row_decoder_inst[port].by()
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y_off -= (self.bank_select.height + drc["well_to_well"])
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self.bank_select_pos = vector(x_off,y_off)
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self.bank_select_inst[port].place(self.bank_select_pos)
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@ -590,18 +623,31 @@ class bank(design.design):
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# Precharge has no gnd
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#if inst != self.precharge_array_inst[port]:
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self.copy_layout_pin(inst, "gnd")
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def route_bank_select(self):
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""" Route the bank select logic. """
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for port in range(self.total_ports):
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for input_name in self.input_control_signals+["bank_sel"]:
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self.copy_layout_pin(self.bank_select_inst[port], input_name)
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for gated_name in self.control_signals:
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if self.port_id[port] == "rw":
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bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "s_en", "bank_sel"]
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gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en", "gated_s_en"]
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elif self.port_id[port] == "w":
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bank_sel_signals = ["clk_buf", "clk_buf_bar", "w_en", "bank_sel"]
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gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_w_en"]
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else:
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bank_sel_signals = ["clk_buf", "clk_buf_bar", "s_en", "bank_sel"]
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gated_bank_sel_signals = ["gated_clk_buf", "gated_clk_buf_bar", "gated_s_en"]
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copy_control_signals = self.input_control_signals[port]+["bank_sel{}".format(port)]
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for signal in range(len(copy_control_signals)):
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self.copy_layout_pin(self.bank_select_inst[port], bank_sel_signals[signal], copy_control_signals[signal])
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for signal in range(len(gated_bank_sel_signals)):
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# Connect the inverter output to the central bus
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out_pos = self.bank_select_inst[port].get_pin(gated_name).rc()
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bus_pos = vector(self.bus_xoffset[gated_name].x, out_pos.y)
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out_pos = self.bank_select_inst[port].get_pin(gated_bank_sel_signals[signal]).rc()
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name = self.control_signals[port][signal]
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bus_pos = vector(self.bus_xoffset[name].x, out_pos.y)
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self.add_path("metal3",[out_pos, bus_pos])
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=bus_pos,
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@ -619,7 +665,8 @@ class bank(design.design):
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After the modules are instantiated, find the dimensions for the
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control bus, power ring, etc.
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"""
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# FIXME: calculate for multiport
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#The minimum point is either the bottom of the address flops,
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#the column decoder (if there is one).
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write_driver_min_y_offset = self.write_driver_array_inst[0].by() - 3*self.m2_pitch
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@ -653,7 +700,6 @@ class bank(design.design):
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self.height = ur.y - ll.y
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self.width = ur.x - ll.x
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def route_central_bus(self):
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""" Create the address, supply, and control signal central bus lines. """
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@ -662,16 +708,16 @@ class bank(design.design):
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# and control lines.
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# The bank is at (0,0), so this is to the left of the y-axis.
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# 2 pitches on the right for vias/jogs to access the inputs
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control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset)
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control_bus_length = self.max_y_offset - self.min_y_offset
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self.bus_xoffset = self.create_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=control_bus_offset,
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names=self.control_signals,
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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for port in range(self.total_ports):
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control_bus_offset = vector(-self.m2_pitch * self.num_control_lines - self.m2_width, self.min_y_offset)
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control_bus_length = self.max_y_offset - self.min_y_offset
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self.bus_xoffset = self.create_bus(layer="metal2",
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pitch=self.m2_pitch,
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offset=control_bus_offset,
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names=self.control_signals[port],
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length=control_bus_length,
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vertical=True,
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make_pins=(self.num_banks==1))
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def route_precharge_to_bitcell_array(self):
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@ -712,7 +758,8 @@ class bank(design.design):
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vector(bitcell_bl.x,yoffset), bitcell_bl])
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self.add_path("metal2",[col_mux_br, vector(col_mux_br.x,yoffset),
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vector(bitcell_br.x,yoffset), bitcell_br])
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def route_sense_amp_to_col_mux_or_bitcell_array(self):
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""" Routing of BL and BR between sense_amp and column mux or bitcell array """
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@ -736,61 +783,61 @@ class bank(design.design):
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vector(connect_bl.x,yoffset), connect_bl])
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self.add_path("metal2",[sense_amp_br, vector(sense_amp_br.x,yoffset),
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vector(connect_br.x,yoffset), connect_br])
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def route_sense_amp_out(self):
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""" Add pins for the sense amp output """
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# FIXME: Update for multiport
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for bit in range(self.word_size):
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data_pin = self.sense_amp_array_inst[0].get_pin("data[{}]".format(bit))
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self.add_layout_pin_rect_center(text="dout0[{}]".format(bit),
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layer=data_pin.layer,
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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for port in range(self.total_read):
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for bit in range(self.word_size):
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data_pin = self.sense_amp_array_inst[port].get_pin("data[{}]".format(bit))
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self.add_layout_pin_rect_center(text="dout{0}[{1}]".format(self.read_index[port],bit),
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layer=data_pin.layer,
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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def route_row_decoder(self):
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""" Routes the row decoder inputs and supplies """
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# FIXME: Update for multiport
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# Create inputs for the row address lines
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for row in range(self.row_addr_size):
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addr_idx = row + self.col_addr_size
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decoder_name = "addr[{}]".format(row)
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addr_name = "addr0[{}]".format(addr_idx)
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self.copy_layout_pin(self.row_decoder_inst[0], decoder_name, addr_name)
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for port in range(self.total_ports):
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for row in range(self.row_addr_size):
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addr_idx = row + self.col_addr_size
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decoder_name = "addr[{}]".format(row)
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addr_name = "addr{0}[{1}]".format(port,addr_idx)
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self.copy_layout_pin(self.row_decoder_inst[port], decoder_name, addr_name)
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def route_write_driver(self):
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""" Connecting write driver """
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for row in range(self.word_size):
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data_name = "data[{}]".format(row)
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din_name = "din0[{}]".format(row)
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self.copy_layout_pin(self.write_driver_array_inst[0], data_name, din_name)
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for port in range(self.total_ports):
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for row in range(self.word_size):
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data_name = "data[{}]".format(row)
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din_name = "din{0}[{1}]".format(port,row)
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self.copy_layout_pin(self.write_driver_array_inst[port], data_name, din_name)
|
||||
|
||||
|
||||
def route_wordline_driver(self):
|
||||
""" Connecting Wordline driver output to Bitcell WL connection """
|
||||
for port in range(self.total_ports):
|
||||
for row in range(self.num_rows):
|
||||
# The pre/post is to access the pin from "outside" the cell to avoid DRCs
|
||||
decoder_out_pos = self.row_decoder_inst[port].get_pin("decode[{}]".format(row)).rc()
|
||||
driver_in_pos = self.wordline_driver_inst[port].get_pin("in[{}]".format(row)).lc()
|
||||
mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0)
|
||||
mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1)
|
||||
self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos])
|
||||
|
||||
for row in range(self.num_rows):
|
||||
# The pre/post is to access the pin from "outside" the cell to avoid DRCs
|
||||
decoder_out_pos = self.row_decoder_inst[0].get_pin("decode[{}]".format(row)).rc()
|
||||
driver_in_pos = self.wordline_driver_inst[0].get_pin("in[{}]".format(row)).lc()
|
||||
mid1 = decoder_out_pos.scale(0.5,1)+driver_in_pos.scale(0.5,0)
|
||||
mid2 = decoder_out_pos.scale(0.5,0)+driver_in_pos.scale(0.5,1)
|
||||
self.add_path("metal1", [decoder_out_pos, mid1, mid2, driver_in_pos])
|
||||
|
||||
# The mid guarantees we exit the input cell to the right.
|
||||
driver_wl_pos = self.wordline_driver_inst[0].get_pin("wl[{}]".format(row)).rc()
|
||||
bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.total_wl_list[0]+"[{}]".format(row)).lc()
|
||||
mid1 = driver_wl_pos.scale(0.5,1)+bitcell_wl_pos.scale(0.5,0)
|
||||
mid2 = driver_wl_pos.scale(0.5,0)+bitcell_wl_pos.scale(0.5,1)
|
||||
self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos])
|
||||
|
||||
# The mid guarantees we exit the input cell to the right.
|
||||
driver_wl_pos = self.wordline_driver_inst[port].get_pin("wl[{}]".format(row)).rc()
|
||||
bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.total_wl_list[port]+"[{}]".format(row)).lc()
|
||||
mid1 = driver_wl_pos.scale(0.5,1)+bitcell_wl_pos.scale(0.5,0)
|
||||
mid2 = driver_wl_pos.scale(0.5,0)+bitcell_wl_pos.scale(0.5,1)
|
||||
self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos])
|
||||
|
||||
|
||||
def route_column_address_lines(self):
|
||||
|
|
@ -798,49 +845,45 @@ class bank(design.design):
|
|||
if not self.col_addr_size>0:
|
||||
return
|
||||
|
||||
|
||||
|
||||
if self.col_addr_size == 1:
|
||||
|
||||
# Connect to sel[0] and sel[1]
|
||||
decode_names = ["Zb", "Z"]
|
||||
|
||||
# The Address LSB
|
||||
self.copy_layout_pin(self.col_decoder_inst[0], "A", "addr0[0]")
|
||||
|
||||
elif self.col_addr_size > 1:
|
||||
decode_names = []
|
||||
for i in range(self.num_col_addr_lines):
|
||||
decode_names.append("out[{}]".format(i))
|
||||
|
||||
for i in range(self.col_addr_size):
|
||||
decoder_name = "in[{}]".format(i)
|
||||
addr_name = "addr0[{}]".format(i)
|
||||
self.copy_layout_pin(self.col_decoder_inst[0], decoder_name, addr_name)
|
||||
for port in range(self.total_ports):
|
||||
if self.col_addr_size == 1:
|
||||
|
||||
# Connect to sel[0] and sel[1]
|
||||
decode_names = ["Zb", "Z"]
|
||||
|
||||
# The Address LSB
|
||||
self.copy_layout_pin(self.col_decoder_inst[port], "A", "addr{}[0]".format(port))
|
||||
|
||||
elif self.col_addr_size > 1:
|
||||
decode_names = []
|
||||
for i in range(self.num_col_addr_lines):
|
||||
decode_names.append("out[{}]".format(i))
|
||||
|
||||
# This will do a quick "river route" on two layers.
|
||||
# When above the top select line it will offset "inward" again to prevent conflicts.
|
||||
# This could be done on a single layer, but we follow preferred direction rules for later routing.
|
||||
top_y_offset = self.col_mux_array_inst[0].get_pin("sel[{}]".format(self.num_col_addr_lines-1)).cy()
|
||||
for (decode_name,i) in zip(decode_names,range(self.num_col_addr_lines)):
|
||||
mux_name = "sel[{}]".format(i)
|
||||
mux_addr_pos = self.col_mux_array_inst[0].get_pin(mux_name).lc()
|
||||
|
||||
decode_out_pos = self.col_decoder_inst[0].get_pin(decode_name).center()
|
||||
for i in range(self.col_addr_size):
|
||||
decoder_name = "in[{}]".format(i)
|
||||
addr_name = "addr{0}[{1}]".format(port,i)
|
||||
self.copy_layout_pin(self.col_decoder_inst[port], decoder_name, addr_name)
|
||||
|
||||
|
||||
# To get to the edge of the decoder and one track out
|
||||
delta_offset = self.col_decoder_inst[0].rx() - decode_out_pos.x + self.m2_pitch
|
||||
if decode_out_pos.y > top_y_offset:
|
||||
mid1_pos = vector(decode_out_pos.x + delta_offset + i*self.m2_pitch,decode_out_pos.y)
|
||||
else:
|
||||
mid1_pos = vector(decode_out_pos.x + delta_offset + (self.num_col_addr_lines-i)*self.m2_pitch,decode_out_pos.y)
|
||||
mid2_pos = vector(mid1_pos.x,mux_addr_pos.y)
|
||||
#self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
|
||||
self.add_path("metal1",[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
|
||||
|
||||
# This will do a quick "river route" on two layers.
|
||||
# When above the top select line it will offset "inward" again to prevent conflicts.
|
||||
# This could be done on a single layer, but we follow preferred direction rules for later routing.
|
||||
top_y_offset = self.col_mux_array_inst[port].get_pin("sel[{}]".format(self.num_col_addr_lines-1)).cy()
|
||||
for (decode_name,i) in zip(decode_names,range(self.num_col_addr_lines)):
|
||||
mux_name = "sel[{}]".format(i)
|
||||
mux_addr_pos = self.col_mux_array_inst[port].get_pin(mux_name).lc()
|
||||
|
||||
decode_out_pos = self.col_decoder_inst[port].get_pin(decode_name).center()
|
||||
|
||||
|
||||
# To get to the edge of the decoder and one track out
|
||||
delta_offset = self.col_decoder_inst[port].rx() - decode_out_pos.x + self.m2_pitch
|
||||
if decode_out_pos.y > top_y_offset:
|
||||
mid1_pos = vector(decode_out_pos.x + delta_offset + i*self.m2_pitch,decode_out_pos.y)
|
||||
else:
|
||||
mid1_pos = vector(decode_out_pos.x + delta_offset + (self.num_col_addr_lines-i)*self.m2_pitch,decode_out_pos.y)
|
||||
mid2_pos = vector(mid1_pos.x,mux_addr_pos.y)
|
||||
#self.add_wire(("metal1","via1","metal2"),[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
|
||||
self.add_path("metal1",[decode_out_pos, mid1_pos, mid2_pos, mux_addr_pos])
|
||||
|
||||
|
||||
def add_lvs_correspondence_points(self):
|
||||
|
|
@ -894,30 +937,39 @@ class bank(design.design):
|
|||
# From control signal to the module pin
|
||||
# Connection from the central bus to the main control block crosses
|
||||
# pre-decoder and this connection is in metal3
|
||||
connection = []
|
||||
connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst[0].get_pin("en").lc()))
|
||||
connection.append((self.prefix+"w_en0", self.write_driver_array_inst[0].get_pin("en").lc()))
|
||||
connection.append((self.prefix+"s_en", self.sense_amp_array_inst[0].get_pin("en").lc()))
|
||||
|
||||
for (control_signal, pin_pos) in connection:
|
||||
control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y)
|
||||
self.add_path("metal1", [control_pos, pin_pos])
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=control_pos,
|
||||
rotate=90)
|
||||
|
||||
# clk to wordline_driver
|
||||
control_signal = self.prefix+"clk_buf"
|
||||
pin_pos = self.wordline_driver_inst[0].get_pin("en").uc()
|
||||
mid_pos = pin_pos + vector(0,self.m1_pitch)
|
||||
control_x_offset = self.bus_xoffset[control_signal].x
|
||||
control_pos = vector(control_x_offset + self.m1_width, mid_pos.y)
|
||||
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
|
||||
control_via_pos = vector(control_x_offset, mid_pos.y)
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=control_via_pos,
|
||||
rotate=90)
|
||||
write_inst = 0
|
||||
read_inst = 0
|
||||
|
||||
# Control lines for RW ports
|
||||
for port in range(self.total_ports):
|
||||
connection = []
|
||||
if (self.port_id[port] == "rw") or (self.port_id[port] == "r"):
|
||||
connection.append((self.prefix+"clk_buf_bar{}".format(port), self.precharge_array_inst[read_inst].get_pin("en").lc()))
|
||||
if (self.port_id[port] == "rw") or (self.port_id[port] == "w"):
|
||||
connection.append((self.prefix+"w_en{}".format(port), self.write_driver_array_inst[write_inst].get_pin("en").lc()))
|
||||
write_inst += 1
|
||||
if (self.port_id[port] == "rw") or (self.port_id[port] == "r"):
|
||||
connection.append((self.prefix+"s_en{}".format(port), self.sense_amp_array_inst[read_inst].get_pin("en").lc()))
|
||||
read_inst += 1
|
||||
|
||||
for (control_signal, pin_pos) in connection:
|
||||
control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y)
|
||||
self.add_path("metal1", [control_pos, pin_pos])
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=control_pos,
|
||||
rotate=90)
|
||||
|
||||
# clk to wordline_driver
|
||||
control_signal = self.prefix+"clk_buf{}".format(port)
|
||||
pin_pos = self.wordline_driver_inst[port].get_pin("en").uc()
|
||||
mid_pos = pin_pos + vector(0,self.m1_pitch)
|
||||
control_x_offset = self.bus_xoffset[control_signal].x
|
||||
control_pos = vector(control_x_offset + self.m1_width, mid_pos.y)
|
||||
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
|
||||
control_via_pos = vector(control_x_offset, mid_pos.y)
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=control_via_pos,
|
||||
rotate=90)
|
||||
|
||||
|
||||
def analytical_delay(self, slew, load):
|
||||
|
|
|
|||
|
|
@ -15,9 +15,11 @@ class bank_select(design.design):
|
|||
banks are created in upper level SRAM module
|
||||
"""
|
||||
|
||||
def __init__(self, name="bank_select"):
|
||||
def __init__(self, name="bank_select", port="rw"):
|
||||
design.design.__init__(self, name)
|
||||
|
||||
self.port = port
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
|
@ -38,10 +40,17 @@ class bank_select(design.design):
|
|||
def add_pins(self):
|
||||
|
||||
# Number of control lines in the bus
|
||||
self.num_control_lines = 4
|
||||
if self.port == "rw":
|
||||
self.num_control_lines = 4
|
||||
else:
|
||||
self.num_control_lines = 3
|
||||
# The order of the control signals on the control bus:
|
||||
# FIXME: Update for multiport (these names are not right)
|
||||
self.input_control_signals = ["clk_buf", "clk_buf_bar", "w_en0", "s_en"]
|
||||
self.input_control_signals = ["clk_buf", "clk_buf_bar"]
|
||||
if (self.port == "rw") or (self.port == "w"):
|
||||
self.input_control_signals.append("w_en")
|
||||
if (self.port == "rw") or (self.port == "r"):
|
||||
self.input_control_signals.append("s_en")
|
||||
# These will be outputs of the gaters if this is multibank
|
||||
self.control_signals = ["gated_"+str for str in self.input_control_signals]
|
||||
|
||||
|
|
|
|||
|
|
@ -17,8 +17,16 @@ class bank_select_test(openram_test):
|
|||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
import bank_select
|
||||
|
||||
debug.info(1, "No column mux")
|
||||
a = bank_select.bank_select()
|
||||
debug.info(1, "No column mux, rw control logic")
|
||||
a = bank_select.bank_select(port="rw")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "No column mux, w control logic")
|
||||
a = bank_select.bank_select(port="w")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "No column mux, r control logic")
|
||||
a = bank_select.bank_select(port="r")
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
|
|
|||
Loading…
Reference in New Issue