luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Actually changed the noops default data in this commit.

This commit is contained in:
Hunter Nichols 2018-08-30 15:16:54 -07:00
parent 53fa6108e1
commit 907b7310ee
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/characterizer/delay.py
View File

@ -764,7 +764,7 @@ class delay():
self.add_address(address, port)
#This value is hard coded here. May want to make it a member variable or input to give control over this value
#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
noop_data = "0"*self.word_size
#Add noops to all other ports.
for unselected_port in self.readwrite_ports+self.read_ports+self.write_ports:
@ -791,10 +791,12 @@ class delay():
self.add_data(data,port)
self.add_address(address,port)
#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
noop_data = "0"*self.word_size
#Add noops to all other ports.
for readwrite_port in self.readwrite_ports+self.read_ports+self.write_ports:
if readwrite_port != port:
self.add_noop_one_port(address, data, readwrite_port)
self.add_noop_one_port(address, noop_data, readwrite_port)
def gen_test_cycles_one_port(self, read_port, write_port):
"""Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge)