mirror of https://github.com/VLSIDA/OpenRAM.git
Unskipped functional tests and increases the number of ports on pbitcell functional tests.
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@ -20,6 +20,9 @@ class psram_1bank_2mux_func_test(openram_test):
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@ -11,7 +11,7 @@ import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
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#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test")
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class psram_1bank_4mux_func_test(openram_test):
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def runTest(self):
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@ -20,6 +20,9 @@ class psram_1bank_4mux_func_test(openram_test):
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@ -20,6 +20,9 @@ class psram_1bank_8mux_func_test(openram_test):
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@ -20,6 +20,9 @@ class psram_1bank_nomux_func_test(openram_test):
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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