mirror of https://github.com/VLSIDA/OpenRAM.git
Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay.
This commit is contained in:
Hunter Nichols
parent
ab7d3510b5
commit
4586ed343f
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@ -203,76 +203,64 @@ class delay():
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self.sf.close()
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def get_delay_meas_values(self, delay_name, port):
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"""Get the values needed to generate a Spice measurement statement based on the name of the measurement."""
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debug.check('lh' in delay_name or 'hl' in delay_name, "Measure command {0} does not contain direction (lh/hl)")
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trig_clk_name = "clk"
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meas_name="{0}{1}".format(delay_name, port)
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targ_name = "{0}".format("DOUT{0}[{1}]".format(port,self.probe_data))
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half_vdd = 0.5 * self.vdd_voltage
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trig_slew_low = 0.1 * self.vdd_voltage
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targ_slew_high = 0.9 * self.vdd_voltage
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if 'delay' in delay_name:
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trig_dir="RISE"
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trig_val = half_vdd
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targ_val = half_vdd
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trig_name = trig_clk_name
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if 'lh' in delay_name:
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targ_dir="RISE"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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else:
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targ_dir="FALL"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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elif 'slew' in delay_name:
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trig_name = targ_name
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if 'lh' in delay_name:
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trig_val = trig_slew_low
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targ_val = targ_slew_high
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targ_dir = trig_dir = "RISE"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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else:
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trig_val = targ_slew_high
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targ_val = trig_slew_low
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targ_dir = trig_dir = "FALL"
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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else:
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debug.error(1, "Measure command {0} not recognized".format(delay_name))
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return (meas_name,trig_name,targ_name,trig_val,targ_val,trig_dir,targ_dir,trig_td,targ_td)
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def write_delay_measures_read_port(self, port):
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"""
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Write the measure statements to quantify the delay and power results for a read port.
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"""
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# Trigger on the clk of the appropriate cycle
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trig_clk_name = trig_name = "clk"
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#Target name should be an input to the function or a member variable. That way, the ports can be singled out for testing
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targ_name = "{0}".format("DOUT{0}[{1}]".format(port,self.probe_data))
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trig_val = targ_val = 0.5 * self.vdd_voltage
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trig_delay_val = targ_delay_val = 0.5 * self.vdd_voltage
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trig_slew_low = 0.1 * self.vdd_voltage
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targ_slew_high = 0.9 * self.vdd_voltage
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trig_dir = "FALL"
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targ_dir = "RISE"
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trig_td = targ_td = 0
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parse_error = False
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# Delay the target to measure after the negative edge
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# add measure statements for delays/slews
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for dname in self.delay_meas_names:
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if 'delay' in dname:
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trig_dir="RISE"
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trig_val = trig_delay_val
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targ_val = targ_val
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trig_name = trig_clk_name
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if 'lh' in dname:
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targ_dir="RISE"
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else:
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targ_dir="FALL"
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elif 'slew' in dname:
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trig_name = targ_name
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if 'lh' in dname:
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trig_val = trig_slew_low
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targ_val = targ_slew_high
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targ_dir = trig_dir = "RISE"
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else:
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trig_val = targ_slew_high
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targ_val = trig_slew_low
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targ_dir = trig_dir = "FALL"
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else:
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debug.error(1, "Measure command {0} not recognized".format(dname))
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meas_values = self.get_delay_meas_values(dname, port)
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self.stim.gen_meas_delay(*meas_values)
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if 'lh' in dname:
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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elif 'hl' in dname:
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trig_td = targ_td = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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else:
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debug.error(1, "Measure command {0} does not contain direction (lh/hl)".format(dname))
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self.stim.gen_meas_delay(meas_name="{0}{1}".format(dname, port),
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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targ_val=targ_val,
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trig_dir=trig_dir,
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targ_dir=targ_dir,
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trig_td=trig_td,
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targ_td=targ_td)
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# add measure statements for power
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for pname in self.power_meas_names:
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if "read" not in pname:
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continue
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t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1]
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#Different naming schemes are used for the measure cycle dict and measurement names.
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#TODO: make them the same so they can be indexed the same.
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if '1' in pname:
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t_initial = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read1_{0}".format(port)]+1]
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elif '0' in pname:
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t_initial = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]]
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t_final = self.cycle_times[self.measure_cycles["read0_{0}".format(port)]+1]
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self.stim.gen_meas_power(meas_name="{0}{1}".format(pname, port),
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t_initial=t_initial,
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t_final=t_final)
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@ -429,7 +417,7 @@ class delay():
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include leakage of all cells.
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"""
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#Sanity Check
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debug.check(self.period > 0, "Initial starting period not defined")
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debug.check(self.period > 0, "Target simulation period non-positive")
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result = [{} for i in range(self.total_port_num)]
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# Checking from not data_value to data_value
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@ -645,7 +633,7 @@ class delay():
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Main function to characterize an SRAM for a table. Computes both delay and power characterization.
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"""
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#Dict to hold all characterization values
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char_data = {}
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char_sram_data = {}
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self.set_probe(probe_address, probe_data)
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@ -681,18 +669,17 @@ class delay():
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min_period = self.find_min_period(feasible_delays)
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debug.check(type(min_period)==float,"Couldn't find minimum period.")
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debug.info(1, "Min Period Found: {0}ns".format(min_period))
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char_data["min_period"] = round_time(min_period)
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char_sram_data["min_period"] = round_time(min_period)
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# 3) Find the leakage power of the trimmmed and UNtrimmed arrays.
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(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
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char_data["leakage_power"]=full_array_leakage
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char_sram_data["leakage_power"]=full_array_leakage
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leakage_offset = full_array_leakage - trim_array_leakage
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# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
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load_slew_data = self.simulate_loads_and_slews(slews, loads, leakage_offset)
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#char_data.update(load_slew_data)
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char_port_data = self.simulate_loads_and_slews(slews, loads, leakage_offset)
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return (char_data, load_slew_data)
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return (char_sram_data, char_port_data)
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def simulate_loads_and_slews(self, slews, loads, leakage_offset):
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"""Simulate all specified output loads and input slews pairs of all ports"""
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@ -979,18 +966,18 @@ class delay():
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debug.info(1,"Dynamic Power: {0} mW".format(power.dynamic))
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debug.info(1,"Leakage Power: {0} mW".format(power.leakage))
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data = {"min_period": 0,
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"delay_lh0": delay_lh,
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"delay_hl0": delay_hl,
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"slew_lh0": slew_lh,
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"slew_hl0": slew_hl,
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"read0_power0": power.dynamic,
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"read1_power0": power.dynamic,
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"write0_power0": power.dynamic,
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"write1_power0": power.dynamic,
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"leakage_power": power.leakage
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}
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return data
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sram_data = { "min_period": 0,
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"leakage_power": power.leakage}
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port_data = [{"delay_lh": delay_lh,
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"delay_hl": delay_hl,
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"slew_lh": slew_lh,
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"slew_hl": slew_hl,
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"read0_power": power.dynamic,
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"read1_power": power.dynamic,
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"write0_power": power.dynamic,
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"write1_power": power.dynamic,
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}]
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return (sram_data,port_data)
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def gen_data(self):
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""" Generates the PWL data inputs for a simulation timing test. """
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@ -161,7 +161,7 @@ class lib:
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# Leakage is included in dynamic when macro is enabled
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self.lib.write(" leakage_power () {\n")
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self.lib.write(" when : \"{0}\";\n".format(control_str))
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self.lib.write(" value : {};\n".format(self.char_results["leakage_power"]))
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self.lib.write(" value : {};\n".format(self.char_sram_results["leakage_power"]))
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self.lib.write(" }\n")
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self.lib.write(" cell_leakage_power : {};\n".format(0))
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@ -347,16 +347,16 @@ class lib:
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self.lib.write(" related_pin : \"clk\"; \n")
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self.lib.write(" timing_type : rising_edge; \n")
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self.lib.write(" cell_rise(CELL_TABLE) {\n")
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self.write_values(self.char_results["delay_lh{0}".format(read_port)],len(self.loads)," ")
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self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads)," ")
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self.lib.write(" }\n") # rise delay
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self.lib.write(" cell_fall(CELL_TABLE) {\n")
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self.write_values(self.char_results["delay_hl{0}".format(read_port)],len(self.loads)," ")
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self.write_values(self.char_port_results[read_port]["delay_hl"],len(self.loads)," ")
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self.lib.write(" }\n") # fall delay
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self.lib.write(" rise_transition(CELL_TABLE) {\n")
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self.write_values(self.char_results["slew_lh{0}".format(read_port)],len(self.loads)," ")
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self.write_values(self.char_port_results[read_port]["slew_lh"],len(self.loads)," ")
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self.lib.write(" }\n") # rise trans
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self.lib.write(" fall_transition(CELL_TABLE) {\n")
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self.write_values(self.char_results["slew_hl{0}".format(read_port)],len(self.loads)," ")
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self.write_values(self.char_port_results[read_port]["slew_hl"],len(self.loads)," ")
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self.lib.write(" }\n") # fall trans
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self.lib.write(" }\n") # timing
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self.lib.write(" }\n") # pin
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@ -428,8 +428,8 @@ class lib:
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for port in range(self.total_port_num):
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self.add_clk_control_power(port)
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min_pulse_width = round_time(self.char_results["min_period"])/2.0
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min_period = round_time(self.char_results["min_period"])
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min_pulse_width = round_time(self.char_sram_results["min_period"])/2.0
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min_period = round_time(self.char_sram_results["min_period"])
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_type :\"min_pulse_width\"; \n")
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self.lib.write(" related_pin : clk; \n")
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@ -461,7 +461,7 @@ class lib:
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if port in self.write_ports:
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if port in self.read_ports:
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web_name = " & !WEb{0}".format(port)
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avg_write_power = np.mean(self.char_results["write1_power{0}".format(port)] + self.char_results["write0_power{0}".format(port)])
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avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & clk{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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@ -475,7 +475,7 @@ class lib:
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if port in self.read_ports:
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if port in self.write_ports:
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web_name = " & WEb{0}".format(port)
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avg_read_power = np.mean(self.char_results["read1_power{0}".format(port)] + self.char_results["read0_power{0}".format(port)])
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avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!CSb{0} & !clk{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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@ -502,13 +502,14 @@ class lib:
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if not hasattr(self,"d"):
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self.d = delay(self.sram, self.sp_file, self.corner)
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if self.use_model:
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self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
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char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
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self.char_sram_results, self.char_port_results = char_results
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else:
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probe_address = "1" * self.sram.addr_size
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probe_data = self.sram.word_size - 1
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self.char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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self.char_sram_results, self.char_port_results = char_results
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def compute_setup_hold(self):
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""" Do the analysis if we haven't characterized a FF yet """
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# Do the analysis if we haven't characterized a FF yet
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@ -48,12 +48,14 @@ class timing_sram_test(openram_test):
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data, slews, loads)
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data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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data.update(port_data[0])
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#Assumes single rw port (6t sram)
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl0': [2.5829000000000004],
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'delay_lh0': [0.2255964],
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golden_data = {'delay_hl': [2.5829000000000004],
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'delay_lh': [0.2255964],
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'leakage_power': 0.0019498999999999996,
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'min_period': 4.844,
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'read0_power0': [0.055371399999999994],
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@ -63,16 +65,16 @@ class timing_sram_test(openram_test):
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'write0_power0': [0.06545659999999999],
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'write1_power0': [0.057846299999999996]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl0': [3.452],
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'delay_lh0': [1.3792000000000002],
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golden_data = {'delay_hl': [3.452],
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'delay_lh': [1.3792000000000002],
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'leakage_power': 0.0257065,
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'min_period': 4.688,
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'read0_power0': [15.0755],
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'read1_power0': [14.4526],
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'slew_hl0': [0.6137363],
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'slew_lh0': [0.3381045],
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'write0_power0': [16.9203],
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'write1_power0': [15.367]}
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'read0_power': [15.0755],
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'read1_power': [14.4526],
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'slew_hl': [0.6137363],
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'slew_lh': [0.3381045],
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'write0_power': [16.9203],
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'write1_power': [15.367]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@ -48,11 +48,13 @@ class timing_sram_test(openram_test):
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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data = d.analyze(probe_address, probe_data, slews, loads)
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data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl0': [2.584251],
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'delay_lh0': [0.22870469999999998],
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golden_data = {'delay_hl': [2.584251],
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'delay_lh': [0.22870469999999998],
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'leakage_power': 0.0009567935,
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'min_period': 4.844,
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'read0_power0': [0.0547588],
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@ -62,16 +64,16 @@ class timing_sram_test(openram_test):
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'write0_power0': [0.06513271999999999],
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'write1_power0': [0.058057000000000004]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl0': [3.644147],
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'delay_lh0': [1.629815],
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golden_data = {'delay_hl': [3.644147],
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'delay_lh': [1.629815],
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'leakage_power': 0.0009299118999999999,
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'min_period': 4.688,
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'read0_power0': [16.28732],
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'read1_power0': [15.75155],
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'slew_hl0': [0.6722473],
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'slew_lh0': [0.3386347],
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'write0_power0': [18.545450000000002],
|
||||
'write1_power0': [16.81084]}
|
||||
'read0_power': [16.28732],
|
||||
'read1_power': [15.75155],
|
||||
'slew_hl': [0.6722473],
|
||||
'slew_lh': [0.3386347],
|
||||
'write0_power': [18.545450000000002],
|
||||
'write1_power': [16.81084]}
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue